METHOD AND SYSTEM FOR VISUAL IMPLEMENTATION OF LAYOUT STRUCTURES FOR AN INTEGRATED CIRCUIT
Granted: July 2, 2009
Application Number:
20090172626
The present approach is directed to an improved method, system, and computer program product for visually presenting layout options for generating an electronic design. The visual presentation could be employed to display a set of layout choices when correcting errors or rules violations identified in the design. Alternatively, the visual presentation could be employed to display layout choices during the initial design entry phase for the electronic design.
Method and System for Utilizing Hard and Preferred Rules for C-Routing of Electronic Designs
Granted: July 2, 2009
Application Number:
20090172628
An improved approach for implementing C-routing is described. Cost-based analysis is performed to balance the different rule requirements, to optimize the assignment of objects and nets during C-routing.
Method, System, and Computer Program Product for Implementing External Domain Independent Modeling Framework in a System Design
Granted: July 2, 2009
Application Number:
20090172632
Disclosed are a method, system, and computer program product for implementing external domain independent modeling framework in a system design. In some embodiments, the method or system comprises importing an external model in an external format into the framework while substantially preserving some or all of the interpretation of the external model, determining a internal common representation for the external model within the framework, and displaying or storing the internal common…
METHOD AND MECHANISM FOR PERFORMING CLEARANCE-BASED ZONING
Granted: July 2, 2009
Application Number:
20090172625
A method and mechanism is disclosed for identifying spacing and clearance based rule violations in an IC design. Shadows are employed to identify spacing and clearance based rule violations. The shadow approach of is particularly useful to identify width-dependent spacing and clearance violations, while avoiding false positives that exist with alternate approaches. The embodiments can be used with any type, configuration, or shape of layout objects.
Method and System for Implementing a Complex System or Process
Granted: June 25, 2009
Application Number:
20090164184
The present approach models a process as a series of steps corresponding to sets of inputs and outputs, where the inputs relates to various configurations of elements for a given step of the process. For each step in the process, one or more models are constructed that correspond to the possible parameters and samples associated with specific stages of the process. Sampling is performed to generate raw data for the models. Experimentation is performed on a significant scale to identify a…
Method and System for Verifying Electronic Designs Having Software Components
Granted: June 25, 2009
Application Number:
20090164193
Disclosed is a method and system for providing an improved and flexible approach for handling models of hardware and software designs for verification activities. The semantics of the software and hardware are mapped to allow correct interfacing between the hardware and software models. This allows designers to more efficiently and accurately perform hardware/software co-verification.
Method and System for Implementing Top Down Design and Verification of an Electronic Design
Granted: June 25, 2009
Application Number:
20090164968
Disclosed is a method and system for performing design and verification using stepwise refinement techniques, which can also include or be referred to as “top-down” design verification. With the present stepwise refinement approach, the electronic design can be acted upon at different levels of abstraction, but with approximately the same level of resolution at each abstraction level. A strong relationship of consistency exists between the successive abstraction levels of the design.…
Intelligent Pattern Signature Based on Lithography Effects
Granted: June 11, 2009
Application Number:
20090150836
The present invention is directed to an improved method, system, and computer program product for accessing and analyzing patterns in the integrated circuit design. The method, system or computer program product includes generating an intelligent signature for a pattern. The derived pattern signature is an intelligent pattern identifier because it retains only essential information about a pattern that corresponds to lithography printable portions of the pattern. Accordingly, one pattern…
AUTOMATED DEBUGGING METHOD AND SYSTEM FOR OVER-CONSTRAINED CIRCUIT VERIFICATION ENVIRONMENT
Granted: June 4, 2009
Application Number:
20090144681
An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal…
AUTOMATED DEBUGGING METHOD AND SYSTEM FOR OVER-CONSTRAINED CIRCUIT VERIFICATION ENVIRONMENT
Granted: June 4, 2009
Application Number:
20090144683
An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal…
AUTOMATED DEBUGGING METHOD AND SYSTEM FOR OVER-CONSTRAINED CIRCUIT VERIFICATION ENVIRONMENT
Granted: June 4, 2009
Application Number:
20090144680
An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal…
DESIGNING INTEGRATED CIRCUITS FOR YIELD
Granted: June 4, 2009
Application Number:
20090144671
Method and system for designing integrated circuits for yield are described. Integrated circuits are designed for yield by finding worst yield corners based on design, statistical, and environmental variables and optimizing the design in light of the worst yield corners found.
METHOD AND SYSTEM FOR ENHANCING SOFTWARE DOCUMENTATION AND HELP SYSTEMS
Granted: May 28, 2009
Application Number:
20090138519
A method and system for enhancing software documentation and help systems. In one embodiment, a virtual library for a selected combination of tools is created. The virtual library is then linked to the tools in the selected combination of tools. In another embodiment, a combination of tools for designing a complex software system is selected from one or more software releases. The one or more software releases comprises a plurality of available tools. The selected combination of tools…
METHOD AND SYSTEM FOR ENHANCING SOFTWARE DOCUMENTATION AND HELP SYSTEMS
Granted: May 28, 2009
Application Number:
20090138524
A method and system for enhancing software documentation and help systems. In one embodiment, a virtual library for a selected combination of tools is created. The virtual library is then linked to the tools in the selected combination of tools. In another embodiment, a combination of tools for designing a complex software system is selected from one or more software releases. The one or more software releases comprises a plurality of available tools. The selected combination of tools…
SAVING AND RESTARTING DISCRETE EVENT SIMULATIONS
Granted: May 7, 2009
Application Number:
20090119310
Method, system, and computer program product for saving and restarting discrete event simulations are provided. A discrete event simulation of a scenario is performed via a process executing on a system. The process includes one or more application threads. A checkpoint of the process is created at a point in time when a command to save the discrete event simulation of the scenario is received. The checkpoint includes data elements of the process and the one or more application threads…
DISTRIBUTED TEST COMPRESSION FOR INTEGRATED CIRCUITS
Granted: May 7, 2009
Application Number:
20090119559
A method for testing integrated circuits is provided. The method provides for incorporating compression and decompression logic into each sub-component of an integrated circuit, developing test modes that target different sub-components of the integrated circuit, selecting one of the test modes, applying a test pattern to one or more sub-components of the integrated circuit targeted by the one test mode, comparing a response from application of the test pattern to a known good response,…
Method and System for Implementing Controlled Breaks Between Features Using Sub-Resolution Assist Features
Granted: May 7, 2009
Application Number:
20090119634
Disclosed is a method, system, and computer program product for implementing controlled breaks using sub-resolution assist features. Sub-resolution bridging features are added to implement controlled breaks between features on the layout. The bridging features may also be used to facilitate or optimize multiple mask/exposure techniques that split a layout or features on a layout to address pitch problems.
METHOD AND SYSTEM FOR CREATING A BOOLEAN MODEL OF MULTI-PATH AND MULTI-STRENGTH SIGNALS FOR VERIFICATION
Granted: April 30, 2009
Application Number:
20090113363
A system, method, computer program product for verification and equivalence checking. In one approach, the system, method, and computer program product analyzes the switching paths in a manner consistent with circuit functionality to provide a complete application which can verify the complex characteristics in the circuits to the accurate RTL model function, including FPGA, ROM Arrays, RAM circuits, and other custom integrated circuit designs.
METHOD AND MECHANISM FOR PERFORMING TIMING AWARE VIA INSERTION
Granted: April 30, 2009
Application Number:
20090113366
A method and system to insert redundant vias while preserving timing is disclosed. The system and method preserve the timing during redundant via insertion, which utilizes incremental timing and extraction updates. A budgeting based approach and a path based approach to the method are disclosed. The budgeting approach is faster, while the path based method has a better insight of the worst slack/slew for the entire design.
REGISTRY FOR ELECTRONIC DESIGN AUTOMATION OF INTEGRATED CIRCUITS
Granted: April 30, 2009
Application Number:
20090113369
A method for registering constraints for EDA (Electronic Design Automation) of an IC (Integrated circuit) includes: associating a constraint with values for constraint identification that identify the constraint in an IC design; associating the constraint with values for constraint relationships that relate the constraint to at least one EDA application; saving the constraint identification values and the constraint relationship values in a constraint registry element; and providing an…
