Concurrent optimization of 3D-IC with asymmetrical routing layers
Granted: March 15, 2022
Patent Number:
11276677
Disclosed is an approach to implement multi-die concurrent placement, routing, and/or optimization across multiple dies. This permits the multiple dies to be modeled as a single 3D space. Instead of being limited to a 2D plane, a cell can be placed to the area of any of the dies without splitting the netlist beforehand.
System, method, and computer program product for group and isolation prediction using machine learning and applications in analog placement and sizing
Granted: March 15, 2022
Patent Number:
11275882
The present disclosure relates to a computer-implemented method for electronic design is provided. Embodiments may include receiving, using at least one processor, an electronic design schematic and an electronic design layout and analyzing, via machine learning, at least one schematic feature from a pair of devices associated with the electronic design schematic. Embodiments may further include determining, based, at least in part, upon the analyzing, whether the pair of devices should…
System, method, and computer program product for genetic routing in an electronic circuit design
Granted: March 15, 2022
Patent Number:
11275881
The present disclosure relates to a computer-implemented method for electronic design is provided. Embodiments may include receiving, using at least one processor, an electronic design having one or more unoptimized nets. Embodiments may further include applying a genetic algorithm to the electronic design, wherein the genetic algorithm includes a multi-stage routing analysis. A first stage analysis may apply a device-level global routing analysis, a second stage analysis may include an…
Dynamic one-bit multiplexing switch for emulation interconnect
Granted: March 15, 2022
Patent Number:
11275598
The embodiments disclosed herein describe a switching ASIC that provides a dynamic single-bit routing and multiplexing function in an emulation system. The switching ASIC may receive a set of incoming data streams from a first set of emulation devices (e.g., emulation ASICs), disassemble each data stream to the constituent bits, dynamically multiplex the bits, reassemble the multiplexed bits into outgoing data streams, and transmit the outgoing data streams to a second set of emulation…
Capacitive coupling based feedback for decision feedback equalization
Granted: March 8, 2022
Patent Number:
11271782
In some examples, a receiver can include a sampler circuit that can be configured to process a data input signal corresponding to a current bit received at a receiver based on a capacitive weighted signal to compensate for distortion effects that a previously received bit at the receiver has on the data input signal. The receiver can include a capacitive coupling feedback circuit that can be configured to generate the capacitive weighted signal corresponding to a weighted detected bit of…
System and method for real-time detection of direct and indirect connectivity shorts in an electronic circuit design
Granted: March 8, 2022
Patent Number:
11270050
The present disclosure relates to a method for use with an electronic design. Embodiments may include displaying, at a graphical user interface, at least a portion of the electronic design and receiving a selection of a subcircuit at a first position of the graphical user interface. In response to a user input, embodiments may include transitioning the subcircuit from the first position to a second position of the graphical user interface and determining one or more direct and indirect…
System and method for updating shapes associated with an electronic design
Granted: March 1, 2022
Patent Number:
11263381
Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving, using a processor, an electronic design and providing, at a graphical user interface, an option to change an object associated with the electronic design. Embodiments may further include identifying a damage area associated with the electronic design, the damage area including an object therein. Embodiments may also include generating a…
Methods, systems, and computer program product for implementing an electronic design with high-capacity design closure
Granted: February 22, 2022
Patent Number:
11256837
Disclosed are methods, systems, and articles of manufacture for implementing an electronic design with high-capacity design closure. A reduced netlist may be generated for an analysis view of an electronic design based at least in part upon logic of interest in the analysis view. A closure may be performed based at least in part upon a union netlist, wherein the union netlist is generated from the reduced netlist. The electronic design may then be implemented based at least in part upon…
Method and system to implement a composite, multi-domain model for electro-optical modeling and simulation
Granted: February 22, 2022
Patent Number:
11256841
Provided is an improved method, system, and computer program product to implement simulation for photonic devices. A composite, multi-domain simulation model is disclosed, with connected domain-specific representations that allow the use of the most relevant simulator technology for a given domain. The model has external connection points either expressed as actual ports or virtual ones, embodied by simulator API calls in the model.
IP block scan chain construction
Granted: February 22, 2022
Patent Number:
11256839
A scan chain engine can determine a set number of EXTEST scan chains for the IP block and based on a predetermined maximum number of EXTEST wrapper cells per EXTEST scan chain. The scan chain engine iteratively executes partitioning on the IP block to generate a set of partitions. Each partition in the set of partitions has a number of EXTEST wrapper cells that does not exceed the maximum number of EXTEST wrapper cells per EXTEST scan chain. The scan chain engine selectively merges…
Machine-learning based prediction method for iterative clustering during clock tree synthesis
Granted: February 8, 2022
Patent Number:
11244099
Aspects of the present disclosure address systems and methods for performing a machine-learning based clustering of dock sinks during clock tree synthesis. An integrated circuit design comprising a clock net that includes a plurality of clock sinks is accessed. A set of clusters are generated by clustering the set of clock objects of the clock net. A machine-learning model is used to assess whether each cluster satisfies one or more design rule constraints. Based on determining each…
Framing protocol supporting low-latency serial interface in an emulation system
Granted: February 8, 2022
Patent Number:
11243856
Using a framing protocol, an application specific integrated circuit (ASIC) in an emulation system may transmit a start-of-packet molecule to a serializer-deserializer (SerDes) interface of a switching ASIC in a gap cycle leading up to an emulation cycle such that the switching ASIC may start routing mission data through the SerDes interface during the emulation cycle. The ASIC may transmit an end-of-packet molecule at a first gap cycle to the SerDes interface of the switching ASIC such…
Transmitter test with interpolation
Granted: February 1, 2022
Patent Number:
11238204
Various embodiments provide for testing a transmitter with interpolation, which can be used with a circuit for data communications, such as serializer/deserializer (SerDes) communications. In particular, some embodiments provide for data transmission test of a transmitter by: generating and outputting a pre-determined data pattern through a serializer of the transmitter; sampling a serialized data output of the serializer over a plurality of different interpolation phase positions of a…
Clock calibration for data serializer
Granted: January 18, 2022
Patent Number:
11228416
Various embodiments provide for calibrating one or more clock signals for a serializer, which can be used with a circuit for data communications, such as serializer/deserializer (SerDes) communications. In particular, for a serializer operating based on a plurality of clock signals, some embodiments provide for calibration of one or more of the plurality of clock signals by adjusting a duty cycle of one or more clock signals, a delay of one or more clock signals, or both.
System, method, and computer program product for distributed learning in an electronic design
Granted: January 18, 2022
Patent Number:
11227087
The present disclosure relates to embodiments for collaborative electronic design. Embodiments may include receiving a baseline model at a computing device associated with each of a plurality of geographically dispersed electronic design teams. Embodiments may further include applying environmental data from each of the plurality of geographically dispersed electronic design teams to the baseline model. Embodiments may also include generating a plurality of training changes, based upon,…
Method and system for functional safety verification using fault relation rules
Granted: January 4, 2022
Patent Number:
11216606
A computer implemented method for functional safety verification includes simulating SA0 and/or SA1 faults at a Q output port of each sequential element in a first representation of an electronic design, to determine whether any of the simulated faults is detectable by a safety mechanism, determining, based on one or more fault relation rules and based on a second gate-level representation of the electronic design, whether any of the faults is also detectable by the safety mechanism if…
Emulation system supporting four-state for sequential logic circuits
Granted: December 7, 2021
Patent Number:
11194942
An emulation processor may be configured to support emulating unknown binary logic based on non-arbitrariness of the unknown binary logic. For example, an unknown binary logic signal may take the finite binary values of 0 and 1. The circuitry in the emulation processor is configured to generate and propagate outputs based on the interactions of known input binary signals with the unknown input binary signals having non-arbitrary states. The emulation processor may support the both…
Method, system, and product for deferred merge based method for graph based analysis pessimism reduction
Granted: November 30, 2021
Patent Number:
11188696
An approach is described for a method, system, and product for deferred merge based method for graph based analysis to reduce pessimism. According to some embodiments, the approach includes receiving design data, static and/or statistical timing analysis data, identifying cells and interconnects for performing graph based worst case timing analysis where merger of signals is deferred based on one or more conditions to reduce pessimism, and generating results thereof. Other additional…
Dual path level shifter to reduce duty cycle distortion
Granted: November 30, 2021
Patent Number:
11190189
A level shifter circuit comprises a first and second path connected in parallel. The first path comprises three inverters connected in series, and the first path generates a first intermediate clock signal based on an input clock signal. The first intermediate clock signal has a first duty cycle distortion. The second path also comprises three inverters connected in series and the second path generates a second intermediate clock signal based on the input clock signal. The second…
Dynamic weighting scheme for local cluster refinement
Granted: November 30, 2021
Patent Number:
11188702
Aspects of the present disclosure address systems and methods for local cluster refinement for integrated circuit (IC) designs using a dynamic weighting scheme. Initial cluster definitions are accessed. The initial cluster definitions define a plurality of clusters where each cluster includes a plurality of pins. Each cluster is evaluated with respect to one or more design rule constraints. Based on the evaluation, clusters are identified from the plurality of clusters. A set of…
