Data alignment in physical layer device
Granted: November 30, 2021
Patent Number:
11190331
A physical layer (PHY) device comprises a phase interpolator to generate a set of sampler clocks. A sampler of the PHY device samples a calibration data pattern based on the set of sampler clocks. A data alignment system of the PHY device performs a coarse calibration and a fine calibration on the sampler clock signals. During the coarse calibration, the data alignment system moves the sampler clock signals earlier or later in time relative to the sampled data based on a first bit of the…
Dual path level shifter to reduce duty cycle distortion
Granted: November 30, 2021
Patent Number:
11190189
A level shifter circuit comprises a first and second path connected in parallel. The first path comprises three inverters connected in series, and the first path generates a first intermediate clock signal based on an input clock signal. The first intermediate clock signal has a first duty cycle distortion. The second path also comprises three inverters connected in series and the second path generates a second intermediate clock signal based on the input clock signal. The second…
Dynamic weighting scheme for local cluster refinement
Granted: November 30, 2021
Patent Number:
11188702
Aspects of the present disclosure address systems and methods for local cluster refinement for integrated circuit (IC) designs using a dynamic weighting scheme. Initial cluster definitions are accessed. The initial cluster definitions define a plurality of clusters where each cluster includes a plurality of pins. Each cluster is evaluated with respect to one or more design rule constraints. Based on the evaluation, clusters are identified from the plurality of clusters. A set of…
Method, system, and product for deferred merge based method for graph based analysis pessimism reduction
Granted: November 30, 2021
Patent Number:
11188696
An approach is described for a method, system, and product for deferred merge based method for graph based analysis to reduce pessimism. According to some embodiments, the approach includes receiving design data, static and/or statistical timing analysis data, identifying cells and interconnects for performing graph based worst case timing analysis where merger of signals is deferred based on one or more conditions to reduce pessimism, and generating results thereof. Other additional…
Method, system, and product to provide an improved approach to perform polar encoding
Granted: November 23, 2021
Patent Number:
11184111
An approach is described for a method, system, and product, the approach includes setting up a sorted unique value array, receiving a user input, receiving data for polar encoding, generating an output array based on locations determined using the sorted unique value array and values determined using the data for polar encoding, and transmit data using 5g wireless communication protocol that has been processed by polar encoding.
Inline hardware compression subsystem for emulation trace data
Granted: November 16, 2021
Patent Number:
11176018
A trace subsystem of an emulation system may generate differential frame data based upon successive frames. If one compression mode, the trace subsystem may set a flag bit and store differential frame data if there is at least one non-zero bit in the differential frame data. If the differential frame data includes only zero bits, the trace subsystem may set the flag bit without storing the frame data. In another compression mode, the computer may further compress the differential data if…
Transmitter test using phase-lock loop
Granted: November 2, 2021
Patent Number:
11165554
Various embodiments provide for testing a transmitter using a phase-lock loop, which can be used with a circuit for data communications, such as serializer/deserializer (SerDes) communications. In particular, some embodiments provide for data transmission test of a transmitter by: generating and outputting a pre-determined data pattern through a serializer of the transmitter; sampling a serialized data output of the serializer using a sample clock signal generated by an M/N phase-lock…
Static clock calibration in physical layer device
Granted: November 2, 2021
Patent Number:
11165553
A phase interpolator of a physical layer (PHY) device comprise a phase interpolator to generate a set of asynchronous sampler clocks. A sampler of the PHY device samples a calibration data pattern using a first sampler clock from the set of asynchronous sampler clocks. A calibration control component of the PHY device detects a misalignment of a phase relationship among the set of asynchronous sampler clocks based on the sampled data. In response to detecting the misalignment, the…
Generate clock network using inverting integrated clock gate
Granted: November 2, 2021
Patent Number:
11163929
Various embodiments provide for clock network generation for a circuit design using an inverting integrated clock gate (ICG). According to some embodiments, a clock network with one or more inverting ICGs is generated, after a topology of the clock network is defined, by applying a non-inverting ICG-to-inverting ICG transform to one or more nodes of the clock network that comprise a non-inverting ICG. Additionally, according to some embodiments, a clock network is generated bottom-up…
In-system scan test of electronic devices
Granted: October 26, 2021
Patent Number:
11156660
A system for testing of one or more electronic devices is disclosed. In an embodiment, a processor transmits one or more test vectors to the one or more electronic devices. The one or more test vectors are based upon configuration parameters of the processor and input-output parameters of the one or more electronic devices. The processor receives scan vectors from the one or more electronic devices in response to the plurality of test vectors. The processor verifies in-system behavior of…
Method and system for sequential equivalence checking
Granted: October 19, 2021
Patent Number:
11151295
A method for enhancing performance of SEC of two representations of an electronic design (with and without gated clock) includes selecting one or more pairs of correlated flip-flops (FFs), a first FF of each pair in the first representation toggled by the gated clock controlled by an enable combinational logic and a second FF of the pair, correlating to the first FF, in the second representation toggled by the constantly toggling clock. The method also includes defining a modified enable…
Method, system, and product for an improved approach to placement and optimization in a physical design flow
Granted: October 12, 2021
Patent Number:
11144698
An approach is described for a method, system, and product, that includes identification/generation of a synthesized netlist for use in optimization and placement, generation and utilization of multiple uncertainty values for an early clock tree for guiding optimization and placed of circuit elements in a placeopt process that operates on a path by path basis. In some embodiments, the approach further comprises execution of clock tree synthesis, and routing the synthesized clock tree. In…
Method and system for generating verification tests at runtime
Granted: October 12, 2021
Patent Number:
11144693
A method includes generating on a host machine a validated verification test scenario comprising a graph defining a scheduled performance order of a plurality of actions to be performed on a DUT and a corresponding verification environment; obtaining a subset of one or more actions to be added to the validated scenario while maintaining the plurality of actions of the validated scenario and the scheduled performance order, forming an amended verification test scenario; and applying a…
Formal verification with EDA application and hardware prototyping platform
Granted: October 5, 2021
Patent Number:
11138357
A formal verification EDA application can be configured to receive a circuit design of an IC chip. The circuit design of the IC chip comprises a set of properties for the IC chip and constraints for the IC chip. The formal verification EDA application generates an array of CNF files based on the circuit design of the IC chip. Each CNF file can include a Boolean expression that characterizes a selected property of the set of properties and data fields characterizing initial states for…
Unreachable cover root cause search
Granted: October 5, 2021
Patent Number:
11138355
A formal verification EDA application can be configured to receive a circuit design of an IC chip, the circuit design of the IC chip including a list of properties for the IC chip. The list of properties includes a list of covers for the IC chip. The formal verification engine can also execute a formal verification of the IC chip. Results of the formal verification identifies a subset of covers of the list of covers that are unreachable. The formal verification engine can further execute…
Phase interpolator with phase adjuster for step resolution
Granted: September 28, 2021
Patent Number:
11133793
Various embodiments provide for phase interpolators with phase adjusters to provide step resolution, which can be used with a circuit such as a data serializer/deserializer circuit. In particular, for some embodiments, a phase interpolator is coupled to a phase adjuster, where the combination of the phase interpolator and the phase adjuster is configured to interpolate between phases in phase adjustment steps at a phase adjustment step resolution. For such embodiments, the phase…
Filtering in trainable networks
Granted: September 28, 2021
Patent Number:
11132619
Some embodiments perform, in a multi-layer neural network in a computing device, a convolution operation on input feature maps with multiple convolutional filters. The convolutional filters have multiple filter precisions. In other embodiments, electronic design automation (EDA) systems, methods, and computer-readable media are presented for adding such a multi-layer neural network into an integrated circuit (IC) design.
Using negative-edge integrated clock gate in clock network
Granted: September 28, 2021
Patent Number:
11132490
Various embodiments provide for clock network generation for a circuit design using a negative-edge integrated clock gate (ICG). According to some embodiments, a clock network with one or more negative-edge ICGs is generated, after a topology of the clock network is defined, by applying a positive-edge ICG-to-negative-edge ICG transform to one or more nodes of the clock network that comprise a positive-edge ICG. Additionally, according to some embodiments, a clock network is generated…
Layer assignment based on wirelength threshold
Granted: September 28, 2021
Patent Number:
11132489
Various embodiments provide for layer assignment of a network of a circuit design based on a wirelength threshold, which can facilitate consideration of timing and electromigration and which may be part of electronic design automation (EDA) of a circuit design. More particularly, some embodiments determine (e.g., calculate) a wirelength threshold for a net (e.g., each net) of a circuit design based on one or more characteristics of the net, and select a layer for at least a portion of…
Hardware-efficient scheduling of packets on data paths
Granted: September 21, 2021
Patent Number:
11128410
Embodiments disclosed are directed to methods for scheduling packets. According to example embodiments the method includes receiving, using a first layer in a communication protocol, a first request from a second layer in the communication protocol. The first request indicates to the first layer to output a data stream that includes a first location for the second layer to include a first control packet. The first layer is at a higher level of abstraction than the second layer. The…
