System and method for repeating a synchronized set of layout geometries
Granted: May 25, 2021
Patent Number:
11017145
Embodiments disclosed are directed to systems and methods for modifying an electronic circuit design. According to embodiments, the method includes generating a circuit element of an electronic circuit layout on a graphical user interface, and generating an array group including a plurality of circuit elements. Each cell of the array group includes the same circuit element, and the array group is generated such that a change in at least one attribute of the array group is applied to each…
Method, system, and computer program product for characterizing electromigration effects in an electronic design
Granted: May 25, 2021
Patent Number:
11017136
Disclosed are methods, systems, and articles of manufacture for characterizing electromigration effects in an electronic design. These techniques determine an electrical characteristic at a port of a portion of an electronic design and select a number of frequencies in the frequency domain for the electrical characteristic. Multiple electric currents through a circuit component in the portion may be determined at least by performing a number of analyses for the number of frequencies. An…
System, method, and computer program product for optimization in an electronic design
Granted: May 11, 2021
Patent Number:
11003825
The present disclosure relates to a computer-implemented method for electronic design is provided. Embodiments may include receiving, using at least one processor, an electronic design and determining an objective function associated with the electronic design. Embodiments may further include optimizing the objective function using Bayesian optimization and generating a best hyper-parameter setting based upon, at least in part, the Bayesian optimization.
Deterministic loop breaking in multi-mode multi-corner static timing analysis of integrated circuits
Granted: May 11, 2021
Patent Number:
11003821
The present embodiments relate to static timing analysis (STA) of circuits. The STA can be carried out concurrently for multiple-mode-multiple-corners (MMMC) for circuits including combinational loops. The STA includes determining hard breaking points in the loop associated with each single-mode-single-corner (SMSC) view. The STA also includes merging constraints of all SMSC views to generate a merged set of constraints. The STA includes running MMMC STA for the circuit based on the…
Systems and methods for synthesizing a circuit architecture for division by constants
Granted: May 4, 2021
Patent Number:
10997336
For a division of a dividend by a constant divider, a circuit architecture may calculate partial remainders. The circuit architecture may implement a tree structure to generate intermediate signals of partial remainders and combine adjacent intermediate signals to generate other partial remainders downstream. The circuit architecture may generate a quotient based on the partial remainders. The circuit architecture may also implement bit shifting and zero-padding on left side of the…
Complexity optimization of trainable networks
Granted: May 4, 2021
Patent Number:
10997502
Some embodiments perform, in a multi-layer neural network in a computing device, optimization of the multi-layer neural network, for example by making a convolutional change with a first plurality of convolutional filters, or by making a connection change of a first plurality of convolutional filters. In other embodiments, electronic design automation (EDA) systems, methods, and computer-readable media are presented for adding such a multi-layer neural network into an integrated circuit…
Routing congestion based on layer-assigned net and placement blockage
Granted: May 4, 2021
Patent Number:
10997352
Various embodiments provide for routing a network of a circuit design based on at least one of a placement blockage or a layer-assigned network of a circuit design. For instance, some embodiments route a network of a circuit design (e.g., clock net, date net) by generating a congestion map based on modeling layer-assigned networks, considering (e.g., accounting for) routing congestion based on a placement blockage of the circuit design, or some combination of both.
System, method, and computer program product for electromigration-aware width spacing pattern tracks
Granted: May 4, 2021
Patent Number:
10997351
Embodiments included herein are directed towards method for electronic design. Embodiments may include receiving, using at least one processor, a placed layout and one or more electronic design simulation datasets including current information associated with at least one pin. Embodiments may further include estimating a width to support the current information associated with the at least one pin and updating a pin size associated with the at least one pin based upon, at least in part,…
Incremental chaining in the presence of anchored figures
Granted: May 4, 2021
Patent Number:
10997349
In the context of electronic design automation and particularly circuit layout design software tools, systems and methods for incremental chaining of circuit devices (or, more generally, “figures,” which can include instances and pins) permit user-interactive abutment and placement. Selection of one or more anchor figures highlights chaining candidates which can be automatically chained to the anchor figure(s) upon selection, as with a single mouse click. As compared to manual…
In-system scan test of chips in an emulation system
Granted: May 4, 2021
Patent Number:
10997343
An emulation system may include an emulator. The emulator may include at least one chip and at least one FPGA. The chip may be associated with the FPGA. The FPGA may operate as a coprocessor to implement in-system scan test of the chip. In a scan mode of the in-system scan test, the coprocessor may transmit one or more in-system test instructions to the chip through its existing connections with the chip. The coprocessor may capture test response data from the chip in response to the one…
Methods, systems, and computer program product for characterizing an electronic design with a schematic driven extracted view
Granted: May 4, 2021
Patent Number:
10997333
Disclosed are methods, systems, and articles of manufacture for characterizing an electronic design with a schematic driven extracted view. These techniques identify a schematic of an electronic design, wherein the schematic exists in one or more design fabrics. These techniques further determine an extracted model for characterizing a behavior of the electronic design based at least in part upon the schematic, determine a hierarchical level in a design fabric of the one or more design…
System and method for computing electrical over-stress of devices associated with an electronic design
Granted: May 4, 2021
Patent Number:
10997332
Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving, using at least one processor, an electronic design schematic and splitting, using the at least one processor, the electronic design schematic into a plurality of subcircuits. Embodiments may further include independently simulating each of the plurality of subcircuits to generate simulation results and analyzing the simulation results to…
Synchronized reset for a circuit emulator
Granted: May 4, 2021
Patent Number:
10996723
A method for providing, based on an emulation schedule, a reset message to multiple circuits is provided. The reset message associates a reset signal with a selected clock cycle for each circuit, in the emulation schedule. The method includes determining a mask for each of the circuits based on the emulation schedule, providing a clock signal to the circuits, the clock signal comprising the selected clock cycle for each circuit, and tuning the reset signal relative to the clock signal…
System and method for multiple device diagnostics and failure grouping
Granted: May 4, 2021
Patent Number:
10996270
Systems and methods for multiple device diagnostics are disclosed herein. Exemplary embodiments provide for a multiple device diagnostic system having a plurality of electronic devices selected for diagnosis based on at least one selection criterion, a diagnosis engine in data communication with a failure database, and a diagnosis results database in data communication with the diagnosis engine. Embodiments further provide that the failure database contains grouped failure data from at…
Delay dependence in physically aware cell cloning
Granted: April 27, 2021
Patent Number:
10990721
Electronic design automation systems, methods, and media are presented for cell cloning during circuit design. In one embodiment, for a circuit design comprising a plurality of flip-flop elements having clock inputs provided by a routing tree, a delay is identified for each flip-flop element. The flip-flop elements are clustered by delay to generate at least two clusters of flip-flop elements. Elements within the clusters are then grouped by physical characteristics to generate delay…
Workload management in hybrid clouds
Granted: April 27, 2021
Patent Number:
10992733
The present embodiments relate generally to workload management and more particularly to a hybrid cloud workload management system and methodology which can effectively manage the execution of tasks of the same workload on both private and public clouds. In embodiments, user tasks are seamlessly and transparently executed on a public cloud if the private cloud does not have the necessary resources available. These and other embodiments automatically detect data dependencies of user tasks…
Encoding and striping technique for DC balancing in single-ended signaling
Granted: April 27, 2021
Patent Number:
10992449
A set of encoders within a transmitter (TX) physical layer (PHY) encode incoming data using a predefined encoder scheme by translating multiple data segments into a set of balanced bit sequences. Each data segment comprises a first number of bits and each balanced bit sequence comprises a second number of bits. A data striping component distributes the set of balanced bit sequences to a set of serializers by routing bits from particular bit positions in each balanced bit sequence to a…
Partition-based circuit analysis and verification
Granted: April 27, 2021
Patent Number:
10990734
Devices, methods, computer readable media, and other embodiments are described for automated formal analysis and verification of a circuit design. One embodiment involves accessing a circuit design and a set of default verification targets for the circuit design. A plurality of partitions for the circuit design are then automatically generated, and a first partition is analyzed to generate a first set of verification targets for the first partition based on the set of default…
Shared timing graph propagation for multi-mode multi-corner static timing analysis
Granted: April 27, 2021
Patent Number:
10990733
According to certain aspects, the present embodiments include techniques for performing a single timing analysis run for a plurality of views representing different modes and/or corners. An embodiment analyzes and maintains relevant timing information that is different for different views, but otherwise maintains the same information for all views. This allows each individual view in a single run to be analyzed in the same manner as separate runs for each separate view, thereby ensuring…
Functional built-in self-test architecture in an emulation system
Granted: April 27, 2021
Patent Number:
10990728
An emulation system may have a built-in self-test circuit to generate one or more built-in self-test instructions. The one or more built-in self-test instructions may be pseudorandom. The one or more built-in self-test instructions may cause one or more emulation processors of the emulation system to generate one or more deterministic outputs. A testing processor of the emulation system may compare the one or more deterministic outputs to detect a faulty emulation processor, a faulty…
