System and method for analyzing one or more electromigration rules associated with an electronic circuit design
Granted: August 10, 2021
Patent Number:
11087064
The present disclosure relates to a method for use with an electronic design. Embodiments may include receiving, using a processor, the electronic design and estimating a wire width associated with the electronic design based upon, at least in part, a current in a wire, a layer of the wire, a temperature, and an electromigration length. Embodiments may further include allowing, at a graphical user interface, a user to make an edit to a shape or a layer of the wire and generating a…
System, method, and computer program product for the integration of machine learning predictors in an automatic placement associated with an electronic design
Granted: August 10, 2021
Patent Number:
11087060
The present disclosure relates to a computer-implemented method for electronic design. Embodiments may include receiving, using at least one processor, an electronic design schematic and an electronic design layout and training a model using at least one predictor associated with the electronic design layout. Embodiments may further include obtaining an updated model, based upon, at least in part, the training. Embodiments may also include applying the updated model to a second…
Multi-tap hybrid equalization scheme for 24GBPS GDDR6 memory interface transmitter
Granted: August 3, 2021
Patent Number:
11082267
The embodiments described herein provide for a method and system for implementing a multi-tap hybrid-equalization technique devoid of ISI jitter and PSI jitter in the high-speed data path to achieve 24 Gbps operating speed in systems utilizing GDDR6 DRAM. The method includes receiving an original data signal at a first TFFE circuit and receiving an altered data signal at a second TFFE circuit. The method further comprises generating a time-domain-equalized original data signal using a…
Layer assignment and routing based on resistance or capacitance characteristic
Granted: August 3, 2021
Patent Number:
11080457
Various embodiments provide for layer assignment of a network of a circuit design based on a resistance or capacitance characteristic, such as a resistance/capacitance characteristic associated with a layer, a wire, or a via of the circuit design. In particular, various embodiments consider a resistance/capacitance characteristic of a layer, a wire, or a via of a circuit design to determine a set of layers for routing one or more networks of the circuit design, which can enable some…
Method and system for formal bug hunting
Granted: August 3, 2021
Patent Number:
11080448
A method for formal deep bug hunting in a device under test (DUT) may include obtaining a selection of a start state for the DUT; obtaining a selection of one or a plurality of variables that are declared as random variables; for each of said one or a plurality of random variables, generating a sequence of random values in a generation order using a random number generator (RNG); and performing formal verification exploration of the DUT starting at the start state and consecutively…
Concurrent fault co-simulator
Granted: August 3, 2021
Patent Number:
11080444
Devices, methods, computer-readable media, and other embodiments are described for concurrent functional and fault co-simulation of a circuit design. One embodiment involves accessing simulation data for a circuit design made up of a plurality of machine regions. A plurality of faults is selected from the simulation data for co-simulation operations of functional simulation and fault simulation of the circuit design, and functional simulation of the plurality of machine regions is…
Polar decoder processor
Granted: July 13, 2021
Patent Number:
11063614
In some examples, a polar decoder for implementing polar decoding of a codeword can be configured to implement alogarithmic likelihood ratio (LLR), an even bit, and an odd bit buffer, respectively. The polar decoder can be configured to employ a list-to-buffer mapping state register for the LLR buffer for loading LLR values for each path at a given stage of a decoding graph. The polar decoder can be configured to update and store LLR values for each path at the given stage. The polar…
Input-directed constrained random simulation
Granted: July 6, 2021
Patent Number:
11055460
A system and method for input-directed constrained random simulation includes obtaining an initial state for a finite state machine (FSM) that models an electronic circuit design under test (DUT), the initial state assigning values to registers of the device under test, by providing an initial state function I(s) relating to the FSM to a satisfiability problem (SAT) solver to obtain register values that satisfy the initial state function. A random Boolean circuit R(i) is constructed. A…
Dynamic netlist modification of compacted data arrays in an emulation system
Granted: June 29, 2021
Patent Number:
11048843
A compaction circuit in an emulation system may store in a data array emulation data that may be read in subsequent emulation steps. For each emulation step, the compaction circuit may receive keeptags from a local control store word of the emulation step and store portions of emulation data identified by the keeptags. The keeptags in the control store words may be inserted by a compiler based upon whether a corresponding read port of emulation processor reads the stored data in the…
System, method and computer program product for automatic generation of sizing constraints by reusing existing electronic designs
Granted: June 29, 2021
Patent Number:
11048852
The present disclosure relates to a computer-implemented method for electronic circuit design. Embodiments may include receiving, using at least one processor, data corresponding to an electronic design schematic. Embodiments may further include analyzing the data to learn one or more device size parameters, a range of parameters, or a matching relationship of parameters based upon, at least in part, the electronic design schematic or the electronic design layout, wherein analyzing…
Dynamic width-space patterns for handling complex DRC rules
Granted: June 22, 2021
Patent Number:
11042684
Embodiments according to the present disclosure relate to physically implementing an integrated circuit design using track patterns while conforming to the requirements of complex color based track systems, and using information about instances that have been included in the design. According to some aspects, the present embodiments provide “Dynamic Width Space Patterns (DWSP)” which are WSPs that are modified dynamically in consideration of neighboring geometries such that shapes…
Systems and methods for high-speed data transfer over a communication interface
Granted: June 22, 2021
Patent Number:
11042500
A SPI master may configure a set of hardware registers associated with a SPI client with a set of communication parameters. The SPI master may send a message to the SPI client. The SPI master may periodically ping the SPI client until the SPI master receives an acknowledgement message from the SPI client in response to the message from the SPI master. The SPI master may periodically ping the SPI client based upon the set of communication parameters. The SPI client may transmit the…
Method and apparatus to accelerate verification signoff by selective re-use of integrated coverage models
Granted: June 15, 2021
Patent Number:
11036906
In the context of electronic design automation and in particular coverage-driven verification, each of a number of integrated coverage models to be merged for coverage analysis are divided between a code coverage model and a functional coverage model. During a coverage model generation phase, new code coverage models or functional coverage models are created only if they are not already in a coverage model database repository; otherwise, they are copied. During a merging phase, code…
Track assignment by dynamic programming
Granted: June 8, 2021
Patent Number:
11030378
Various embodiments described herein provide for track assignment of wires of a network of a circuit design by dynamic programming. In particular, various embodiments use a dynamic programming process to determine a set of breaking points for a routing wire of a global-routed and layer-assigned circuit design, and to determine track assignments for each of the sub-wires (sub-routes) formed by applying the set of selected breaking points to the routing wire. This results in a set of…
Routing based on pin placement within routing blockage
Granted: June 8, 2021
Patent Number:
11030377
Various embodiments described herein provide for routing of wires of a network of a circuit design based on pin placement within a routing blockage. In particular, various embodiments provide a routing solution for a circuit design with zero blockage violation when there is no pin inside routing blockage of the circuit design, and uses a parameter (e.g., an adjustable parameter) that controls accuracy at which a routing process handles a pin (e.g., as placed by a placement stage) in…
Method and system for sequential equivalence checking
Granted: June 1, 2021
Patent Number:
11023357
A method for sequential equivalence checking (SEC) of two representations of an electronic design may include using a processor, automatically selecting a plurality of cutpoints in the two representations of the electronic design; using a processor, automatically executing a prove-from strategy on the plurality of cut point pairs to identify a failed cut point pair in the two electronic designs; and using the processor, automatically extending a trace corresponding to the identified…
Method, system, and product to efficiently route interconnections following a free form contour
Granted: June 1, 2021
Patent Number:
11023645
An approach is described for a method, system, and product for detection of contours for data pads of a device having a free form contour, clustering integrated circuit pads and data pads, performing any angle routing based on a contour angle, and performing resistance balancing. For example, data pads of a display device having one or more curved contours (e.g. data pads arranged on an arc) are identified. Corresponding data pads and integrated circuit pads are then grouped together for…
Methods, systems, and computer program product for characterizing timing behavior of an electronic design with a derived current waveform
Granted: June 1, 2021
Patent Number:
11023640
Disclosed are methods, systems, and articles of manufacture for characterizing timing behavior of an electronic design with a derived current waveform. A set of inputs is determined from a set of electrical characteristics of an electronic design or a portion thereof. Moreover, A derived current waveform is determined at one or more modules stored in memory and executing in conjunction with a microprocessor of a computing node based at least in part upon the set of inputs. The electronic…
Hybrid deferred assertion for circuit design
Granted: June 1, 2021
Patent Number:
11023637
A logic simulation electronic design automation (EDA) application, the logic can be configured to receive a circuit design of an integrated circuit (IC) chip, the circuit design comprising an imported module comprising a list of simple immediate assertions (SIAs) for the imported module, wherein the circuit design comprises a first power domain and a second power domain, wherein the first power domain controls a power state of the second power domain and the imported module is assigned…
Methods, systems, and computer program product for characterizing an electronic design with a susceptibility window
Granted: June 1, 2021
Patent Number:
11023636
Disclosed are methods, systems, and articles of manufacture for characterizing an electronic design with a susceptibility window. These techniques identify a set of multiple aggressors in an electronic design and determine, at a susceptibility window module stored in memory and executing in conjunction with a microprocessor of a computing node, a susceptibility window for an internal node of a victim and a timing window for the set of multiple aggressors in the electronic design. These…
