Generating routing structure for clock network based on edge intersection detection
Granted: February 23, 2021
Patent Number:
10929589
Various embodiments provide for generating a routing structure for a clock network based on edge interaction detection, which can facilitate detection/consideration of overuse of routing resources to a balanced routing structure and which may be part of electronic design automation (EDA) of a circuit design. For example, some embodiments use an edge intersection check to detect overuse of routing resources within the routing structure for a clock network.
Methods and systems of enabling concurrent editing of hierarchical electronic circuit layouts
Granted: February 16, 2021
Patent Number:
10922469
Embodiments described herein provide a new layout editor tool allowing designers to concurrently edit various aspects of an electronic circuit layout, even at disparate hierarchical levels of the design. The new layout editor tool enables multiple electronic circuit designers to concurrently edit a layout a different hierarchical levels, by logically establishing editable child sub cell-level partitions within a parent layout-level partition, each of which representing various components…
Circuit modification for efficient electro-static discharge analysis of integrated circuits
Granted: February 16, 2021
Patent Number:
10922456
The present embodiments relate to electrostatic discharge (ESD) simulation of integrated circuit designs. A netlist of the circuit design can be modified to include ESD protection devices and only essential non-ESD devices. The essential non-ESD devices can be determined based on whether a non-ESD device satisfies one or more of two conditions: (i) a least resistance path (LRP) value of at least one terminal of the non-ESD device from any port of the set of ports is less than a first…
Circuit stage credit based approaches to static timing analysis of integrated circuits
Granted: February 9, 2021
Patent Number:
10915685
The present embodiments relate to static timing analysis (STA) of circuits. The STA can include determining graph based analysis (GBA) delays of timing paths within the circuit. Path based analysis (PBA) delays of a subset of timing paths can be determined to generate circuit stage credit values for circuit stages in the circuit. The circuit stage credit values can be used to adjust GBA delays of the timing paths. Prediction functions can be utilized to predict or estimate PBA delays of…
Method, system, and computer program product for characterizing electronic designs with electronic design simplification techniques
Granted: February 2, 2021
Patent Number:
10909302
Disclosed are methods, systems, and articles of manufacture for characterizing electronic designs with electronic design simplification techniques. These techniques identify an input for simplifying an electronic design and generates a simplified electronic design at least by performing layout simplification on the electronic design. A characterization input may be determined for subsequent characterization of the simplified electronic design. An electromagnetic behavior of the…
Method and apparatus for determining waiver applicability conditions and applying the conditions to multiple errors or warnings in physical verification tools
Granted: February 2, 2021
Patent Number:
10909301
An approach is described for determining waiver applicability conditions and applying the conditions to multiple errors or warnings in physical verification tools. According to some embodiments, the approach includes identification of a waiver of an error or warning, registration of one or more condition sets for waiver of an error or warning, waiver of multiple errors or warnings that match the registered one or more condition sets, and further comprise any or all of the following:…
Sampling selection for enhanced high yield estimation in circuit designs
Granted: February 2, 2021
Patent Number:
10909293
A method for performing multiple simulations for a circuit using a first plurality of samples is provided. The method includes obtaining a model of the circuit based on a result of the simulations, determining a failure rate and a confidence interval of the failure rate for the circuit with the performance model. The method includes determining an importance distribution based on the failure rate for the first plurality of samples, wherein the importance distribution is indicative of a…
Hardware assisted weighted toggle count
Granted: February 2, 2021
Patent Number:
10909283
A method for receiving a circuit layout including modules in a hierarchical structure. The method includes selecting a module in the hierarchical structure, identifying multiple toggling netlists in the module during multiple clock cycles, grouping the toggling netlists into clusters based on a toggle weight factor, and finding an average toggle weight factor for each cluster. The method includes generating instrument logic to determine a power consumption of the circuit layout based on…
Power and ground mesh modeling for placement in circuit design
Granted: January 26, 2021
Patent Number:
10902174
Various embodiments provide for modeling a power and ground (PG) mesh for a circuit design placement process. For some embodiments, a reference PG mesh can be used to generate a PG mesh model for a circuit design. A PG mesh model can be generated for a circuit design by calculating how much routing resource is occupied by the reference PG mesh of the circuit design, and the resulting PG mesh model can be applied to the circuit design by removing a similar amount of routing resource from…
Reconfigurable switch for a computing system
Granted: January 26, 2021
Patent Number:
10902177
A reconfigurable switching apparatus may include a plurality of communications transceivers operable to connect to a plurality of programmable integrated circuits. The reconfigurable switching apparatus may further include a plurality of crosspoint switches operably coupled to the plurality of communications transceivers. The reconfigurable switching apparatus may further include a processing circuitry operably coupled to the plurality of crosspoint switches and operable to program the…
Over-constraints for formal verification
Granted: January 19, 2021
Patent Number:
10896277
In the described examples, an electronic design automation formal verification EDA application is configured to receive an initial evaluation of a circuit design of an integrated circuit (IC) chip. The circuit design of the IC chip includes a list of properties for the IC chip, and the list of properties includes a list of assertions for the IC chip. The formal verification EDA program extracts a counter-example trace from the initial evaluation. The counter-example trace characterizes a…
Method, system, and product for generating radial bump patterns
Granted: January 12, 2021
Patent Number:
10891415
An approach is described for a method, system, and product for generating radial bump patterns. According to some embodiments, the approach includes determining parameters for radial pattern generation in a precomputing phase, creating a radial pattern in a second stage, and generating a layout from the radial pattern in the second stage before manufacture a device embodying the radial pattern. In some embodiments, the radial pattern comprises rings having a number of rows where bump…
Memory data transfer and switching sequence
Granted: January 5, 2021
Patent Number:
10885952
Various embodiments described herein provide for a data transfer mechanism for a memory device, such as a Double Data Rate (DDR) memory device, which can improve critical timing within the memory device without a latency impact. In addition, various embodiments described herein provide for a switching sequence for a memory device, which can improve switching time for the memory device.
Routing congestion based on via spacing and pin density
Granted: January 5, 2021
Patent Number:
10885257
Various embodiments provide for routing a network of a circuit design based on at least one of via spacing or pin density. For instance, some embodiments route a net of a circuit design (e.g., data nets, clock nets) by generating a congestion map based on modeling via spacing, modeling pin density, or some combination of both.
Coverage model enhancement to support logic and arithmetic expressions
Granted: January 5, 2021
Patent Number:
10885252
Aspects of the present disclosure address systems and methods for functional coverage in integrated circuit (IC) designs utilizing arbitrary expression to define irrelevant domains in coverage item definitions. A coverage item definition is determined to include an arbitrary expression that defines an irrelevant domain for a coverage item in a functional coverage analysis of an IC design. Based on determining if the item definition comprises the arbitrary expression, a verification the…
Clock gate placement with data path awareness
Granted: January 5, 2021
Patent Number:
10885250
Electronic design automation systems, methods, and media are presented for clock gate placement with data path awareness. One embodiment involves accessing a circuit design with a clock tree, clock gates, and an initial movement area. A set of positions for a set of data path connection points associated with the data routing lines are identified, along with an expansion direction from the initial placement position toward the set of positions for the set of data path connection points,…
Method and system for emulating an image processing system
Granted: January 5, 2021
Patent Number:
10884772
A method for emulating an image processing system on an emulator may include pre-processing of image files that comprises converting each of the image files to a file of low-level image data packets; when emulating the image processing system on the emulator, loading each of the files of low-level image data packets to a memory of the emulator; reading the loaded file from the memory and streaming that file of said files of low-level image data packets to the emulated image processing…
Method and apparatus for a low energy programmable vector processing unit for neural networks backend processing
Granted: January 5, 2021
Patent Number:
10884736
An approach is described for a method and apparatus for a low energy programmable vector processing unit for use in processing such as for example neural network backend processing. According to some embodiments, this approach provides a pooling/vector processing unit for performing backend processing that implements a single issue multiple data (SIMD) datapath that performs various backend processing functions using only a single instruction. For instance, the present approach provides…
Methods, systems, and computer program product for interactively probing a multi-fabric electronic design
Granted: December 29, 2020
Patent Number:
10878164
Disclosed are methods, systems, and articles of manufacture for probing a multi-fabric electronic design that spans across multiple design fabrics. These techniques identify a single layout editor, a first electronic design in a first design fabric, and a second electronic design in a second design fabric. An input for probing a circuit component in the first electronic design may further be identified at a user interface of a computing system. The circuit component being probed is…
Generating lower frequency multi-phase clocks using single high-frequency multi-phase divider
Granted: December 22, 2020
Patent Number:
10873443
According to certain aspects, the present embodiments are directed generally to data communication systems, and more particularly to generating multi-phase clocks in a SerDes system. Embodiments provide SerDes components and methods that are capable of generating multiple different sampling frequencies for parallelizing serial data from a single high speed clock. These and other embodiments can be implemented with circuits that are relatively small and low-power as compared to…
