Methods, systems, and computer program product for reducing interferences and disturbances in a multi-fabric electronic design
Granted: December 22, 2020
Patent Number:
10872192
Disclosed are methods, systems, and articles of manufacture for reducing interferences and disturbances in a multi-fabric electronic design. These techniques identify connectivity for an electronic design that includes design data in multiple design fabrics. One or more interference modules are executed to detect a loop in the electronic design with at least the connectivity. These techniques further execute the one or more interference reduction modules to determine at least one…
Slew rate limited driver with accurate slope
Granted: December 15, 2020
Patent Number:
10868527
Aspects of the present disclosure address a slew rate controlled driver. The slew rate controlled driver includes an amplifier with a capacitive feedback loop and a current generator capable of producing a current that is proportional to on-chip capacitance. The current generator is implemented using a switched capacitor and supplies the driver with a current that is proportional to the capacitance of the switched capacitor. By supplying the driver with current that is proportional to…
Clock pin to clock tap assignment based on circuit device connectivity
Granted: December 8, 2020
Patent Number:
10860775
Various embodiments provide for assigning a clock pin to a clock tap within a circuit design based on connectivity between circuit devices of the circuit design. For some embodiments, an initial clock tap assignment, between a clock tap of a circuit design and a clock pin of the circuit design, is accessed as input, and a modified clock tap assignment (between the clock tap and another clock pin of the circuit design) can be generated based on one or more of the following considerations:…
Systems and methods for transient simulation of circuits with mutual inductors
Granted: December 8, 2020
Patent Number:
10860767
Various embodiments describe performing a transient simulation of circuits that have mutual inductors. In particular, some embodiments perform a transient simulation on a circuit model by removing and approximating the effects of one or more entries of a matrix in the circuit model, where the matrix relates to inductors or mutual inductors of the circuit. In doing so, such embodiments can render the matrix more sparse than before which, in turn, can reduce the time spent during the…
Layer assignment technique to improve timing in integrated circuit design
Granted: December 8, 2020
Patent Number:
10860764
Aspects of the present disclosure address improved systems and methods for layer assignment to improve timing in integrated circuit (IC) designs. An initial placement layout of a net of an IC design is accessed. A plurality of buffer insertion candidates is generated using multiple candidate buffer insertion points and multiple layer assignments from among multiple layers of the IC design. Timing characteristics of each buffer insertion candidate are determined, and timing improvements…
Data routing and multiplexing architecture to support serial links and advanced relocation of emulation models
Granted: December 8, 2020
Patent Number:
10860763
Disclosed herein are systems and methods of compiling resources of a programmable emulation system to execute an emulation process, to emulate a logic system, such as an application-specific integrated circuit (ASIC), currently being tested and prototyped, and then revising, transforming, and moving the compiled instructions sets to inexpensively, quickly, and dynamically adapt to unavailable resources, which may be due to previously allocation to a different emulation job, or for fault…
Multicorner skew scheduling circuit design
Granted: December 8, 2020
Patent Number:
10860757
Electronic design automation systems, methods, and media are presented for slack scheduling. Some embodiments analyzing slack values at the input and output of a circuit element across multiple views. A skew value is then selected which maximizes the slack at the input and output of the circuit element across all views. In some embodiments, this selection operation is streamlined by first identifying skew ranges that preserve a local worst negative slack, and the selected skew value to…
Finding intersections of planar parametric curves based on error-controlled discretization
Granted: December 8, 2020
Patent Number:
10860756
A method includes finding, for a discretized curve comprising multiple segments, first and second segments that are closer than a threshold. The method includes determining an intersection point of the first segment and the second segment, the intersection point associated with a first parameter value for the first segment and a second parameter value for the second segment, determining an error value as a distance between a first point in the parametric curve corresponding to the first…
Sampling selection for enhanced high yield estimation in circuit designs
Granted: December 1, 2020
Patent Number:
10853550
A method for performing multiple simulations for a circuit using a first plurality of samples is provided. The method includes obtaining a model of the circuit based on a result of the simulations, determining a failure rate and a confidence interval of the failure rate for the circuit with the performance model. The method includes determining an importance distribution based on the failure rate for the first plurality of samples, wherein the importance distribution is indicative of a…
System and method for offsetting and smoothing of planar region boundaries defined by arbitrary parametric curves
Granted: December 1, 2020
Patent Number:
10853551
According to an aspect of this disclosure, a computer-implemented method of offsetting boundary curves includes providing a plurality of inputs for an identified boundary set, developing an offset distance, and creating an offset boundary curve for each boundary. The method of offsetting boundary curves further includes determining intersection points of each of the offset boundary curves, assigning a node to each of the intersection points, and determining sections between intersection…
Method and system for sequential equivalence checking
Granted: December 1, 2020
Patent Number:
10853546
A method for sequential equivalence checking (SEC) of two representations of an electronic design includes selecting by a processor a plurality of cutpoints in the two representations of the electronic design, rendering the two representations of the electronic design abstracted; executing by the processor an assume-guarantee (AG) proof on the two abstracted representations of the electronic design; identifying by the processor a failed assertion indicating non-equivalence of a signal…
Automatic gate-level FS analysis and FMEDA
Granted: December 1, 2020
Patent Number:
10853545
Devices, methods, non-transitory computer readable media, and other embodiments are described for automatic gate-level functional safety (FS) analysis and associated circuit design operations. One embodiment involves accessing register transfer level (RTL) design data, and accessing a set of FS data associated with an initial circuit design describing one or more failure modes associated with a plurality of circuit elements, an associated FS design criterion for each failure mode of the…
Systems and methods for creating learning-based personalized user interfaces
Granted: December 1, 2020
Patent Number:
10853100
Systems and methods for creating learning-based personalized user interfaces for software applications are described. Exemplary embodiments provide for collecting usage data and applying machine learning techniques to identify and prioritize certain commands and options in the personalized user interface. The usage data can include Usage patterns, usage sequences, and the usage of certain commands and options in connection with, or following, certain other commands and options may also…
Structure of a high-bandwidth-memory command queue of a memory controller with external per-bank refresh and burst reordering
Granted: December 1, 2020
Patent Number:
10852956
Embodiments of the invention provide a novel structure of a high-bandwidth-memory command queue of a memory controller with external per-bank refresh and DRAM burst reordering. Where the external per-bank refresh removes some of the unpredictable nature of PBR commands and DRAM burst reordering provides for efficient utilization of memory bandwidth.
Multi-modal power control
Granted: December 1, 2020
Patent Number:
10852800
A method includes programming an FPGA based controller of a master blade with a power scheme. The master blade receives a first power management signal from the master blade and slave blades. The master blade transmits a second power management signal to itself and to the slave blades responsive to the first power management signal. The master blade receives a third power management signal from itself and the slave blades. The power scheme controls an order and delay in which the second…
Time based feed forward equalization (TFFE) for high-speed DDR transmitter
Granted: November 24, 2020
Patent Number:
10848352
Circuits, methods and systems that are to be used for dynamically modulating a high frequency bit duration of data based on a status of one or more previous transmitted bits. One circuit comprises a first data path comprising a first input, a first buffer, and a first output connected to a first multiplexer data input. The circuit further comprises a second data path comprising a second input, a second buffer, a phase interpolator, and a second output coupled to a second multiplexer data…
Method and system to implement topology integrity throughout routing implementations
Granted: October 27, 2020
Patent Number:
10817641
Described is an improved approach to implement routing for electrical designs. A structural routing solution is provided, where an automatic routing mechanism is implemented to generate a complete routing tree. The approach captures users' design intent about the topology, and the routing system adhere to that topology intent throughout the layout process.
Method for interactive embedded software debugging through the control of simulation tracing components
Granted: October 13, 2020
Patent Number:
10802852
According to an embodiment, a system and method are provided for supporting interactive debugging of embedded software (ESW) on a simulation platform. A processor model within the simulated system will support a register and memory tracing sub-module. Simulator and emulator breakpoints will be used with the modeled objects within the tracing sub-module. For example, a simulator breakpoint may be set for the task or function that buffers the trace information so it can be written to a…
Methods, systems, and computer program product for implementing an electronic design having embedded circuits
Granted: October 13, 2020
Patent Number:
10803222
Disclosed are methods, systems, and articles of manufacture for implementing an electronic design having embedded circuits. These techniques identify connectivity of an electronic design that includes an embedded circuit, and the embedded circuit is located between a first actual layer and a second actual layer of the electronic design. The electronic design is then transformed, but one or more embedded circuit modules, into a transformed electronic design at least by generating one or…
Method and system for combined formal static analysis of a design code
Granted: October 13, 2020
Patent Number:
10803219
A method for a combined formal static analysis of a design code, the method comprising using a lint checker performing Lint checks to identify a suspected violation in the design code; using a formal static analyzer, performing formal checks to identify a suspected property that corresponds to the suspected violation; applying a formal proof technique to determine whether the suspected property is proven or disproved; and if the suspected property is disproved, issuing an alert.
