Methods, systems, and computer program product for implementing an electronic design having embedded circuits
Granted: October 13, 2020
Patent Number:
10803222
Disclosed are methods, systems, and articles of manufacture for implementing an electronic design having embedded circuits. These techniques identify connectivity of an electronic design that includes an embedded circuit, and the embedded circuit is located between a first actual layer and a second actual layer of the electronic design. The electronic design is then transformed, but one or more embedded circuit modules, into a transformed electronic design at least by generating one or…
Method and system for combined formal static analysis of a design code
Granted: October 13, 2020
Patent Number:
10803219
A method for a combined formal static analysis of a design code, the method comprising using a lint checker performing Lint checks to identify a suspected violation in the design code; using a formal static analyzer, performing formal checks to identify a suspected property that corresponds to the suspected violation; applying a formal proof technique to determine whether the suspected property is proven or disproved; and if the suspected property is disproved, issuing an alert.
Method for interactive embedded software debugging through the control of simulation tracing components
Granted: October 13, 2020
Patent Number:
10802852
According to an embodiment, a system and method are provided for supporting interactive debugging of embedded software (ESW) on a simulation platform. A processor model within the simulated system will support a register and memory tracing sub-module. Simulator and emulator breakpoints will be used with the modeled objects within the tracing sub-module. For example, a simulator breakpoint may be set for the task or function that buffers the trace information so it can be written to a…
EDA CAA with learning phase
Granted: October 6, 2020
Patent Number:
10796067
Systems, methods, media, and other such embodiments described herein relate to critical area analysis (CAA) operations as part of electronic design automation (EDA). One embodiment involves accessing a circuit design having a first layer (which may be a composite layer), sampling the first layer, and performing an initial CAA using the sampled portions of the layer with a set of predetermined defect sizes. The initial CAA is used to automatically generate a model which can be used to…
Power aware resizing of clock tree instances
Granted: October 6, 2020
Patent Number:
10796066
Aspects of the present disclosure address systems and methods for shortening clock-tree wirelength based on target offsets in connected routes. A clock tree comprising routes that interconnect a plurality of clock-tree instances is accessed from memory. A clock-tree instance is selected for evaluation. A baseline power consumption measurement corresponding to a sub-tree of the clock-tree instance with the clock-tree instance at a first size is determined. An alternative power consumption…
Adaptive model interface for a plurality of EDA programs
Granted: October 6, 2020
Patent Number:
10796051
In the described examples, a model impact monitor can include an electronic design automation (EDA) manager that communicates with a plurality of EDA programs, wherein each EDA program generates a model set for a register-transfer level (RTL) design comprising a list of RTL operations. The model impact monitor can also include an adaptive model interface that records changes to the RTL operations of the RTL design and measures a change in performance characteristics of each of the…
Waveform propagation timing modeling for circuit design
Granted: October 6, 2020
Patent Number:
10796049
Electronic design automation systems, methods, and media are presented for a waveform propagation timing model for use with circuit designs and electronic design automation (EDA). One embodiment involves generating a gate output waveform for a circuit element using a driver input signal waveform and then generating a circuit element output waveform using the gate output waveform and an N-pole model of an interconnect with the first circuit element using moment matching. Timing values are…
Partial selection-based model extraction from circuit design layout
Granted: October 6, 2020
Patent Number:
10796042
Various embodiments provide for partial selection-based (e.g., cut-based) model extraction from a layout of a circuit design, which can be used to generate a schematic extracted view for the circuit design and to back annotate a schematic of the circuit design. For some embodiments, the selection comprises a cut of a layout of a circuit design, where the cut may be defined (e.g., inputted) by a user through a graphical user interface that is presenting the layout.
Compacting test patterns for IJTAG test
Granted: October 6, 2020
Patent Number:
10796041
Systems, methods, media, and other such embodiments described herein relate to improved operation of test devices which verify circuit operations. One embodiment involves accessing a circuit design comprising a plurality of instances of one or more blocks, where each block of the one or more blocks is associated with a corresponding block test pattern comprising one or more test subpatterns. Each corresponding block test pattern is processed to identify independent test subpatterns, and…
Characterizing electronic component parameters including on-chip variations and moments
Granted: September 29, 2020
Patent Number:
10789406
The present embodiments are generally directed to electronic circuit design and verification and more particularly to techniques for characterizing electronic components within an electronic circuit design for use in verification. In one or more embodiments, an adaptive sensitivity based analysis is used to build an adaptive equation to represent the timing response surface for an electronic component. With the adaptive surface response built, a sample-based evaluation yields highly…
System, method, and computer program product for generating a formal verification model
Granted: September 29, 2020
Patent Number:
10789404
The present disclosure relates to a method for use in a formal verification of an electronic design. Embodiments may include receiving, using a processor, a specification model associated with an electronic design and generating, using a parser, an intermediate representation based upon, at least in part, the specification model. Embodiments may also include applying a machine generated semantic preserving program transformation to the intermediate representation to create a semantically…
Methods, systems, and computer program product for determining layout equivalence for a multi-fabric electronic design
Granted: September 22, 2020
Patent Number:
10783312
Disclosed are methods, systems, and articles of manufacture for determining layout equivalence between a plurality of versions of a single layout of a multi-fabric electronic design. These techniques identify a first version and a second version of a layout of an electronic design that spans across multiple design fabrics. One or more collaborative comparator modules are executed to determine whether the first version is identical to or different from the second version of the layout.…
System and method for power-grid aware simulation of an IC-package schematic
Granted: September 22, 2020
Patent Number:
10783307
Embodiments include herein are directed towards a method for use in an electronic design environment is provided. The method may include providing, using at least one processor, an electronic circuit design including an integrated circuit (“IC”) or package schematic and generating a power distribution network (“PDN”) based upon at least in part, the electronic circuit design including the IC or package. The method may further include obtaining a PDN model having one or more port…
System, method, and computer program product for handling combinational loops associated with the formal verification of an electronic circuit design
Granted: September 22, 2020
Patent Number:
10783305
The present disclosure relates to a method for electronic circuit design. Embodiments may include providing, using at least one processor, an electronic design and isolating a combinational loop associated with the electronic design. Embodiments may further include inserting a sequential element in a loop path of the combinational loop, wherein the sequential element has a clock that is at least twice as fast as a fastest system clock associated with the electronic design. Embodiments…
System, method, and computer program product for displaying debugging during a formal verification
Granted: September 22, 2020
Patent Number:
10783304
The present disclosure relates to a method for electronic design. Embodiments may include displaying, at a graphical user interface, at least a portion of a cover trace or an assertion counter-example associated with an electronic design. Embodiments may also include allowing, at the graphical user interface, a user to analyze the cover trace or the assertion counter-example during a debugging session. Embodiments may further include identifying a dead-end state during the analysis and…
Systems and methods for extracting hierarchical path exception timing models
Granted: September 22, 2020
Patent Number:
10783300
The present disclosure relates to a system for performing static timing analysis in an electronic design. Embodiments may include providing, using at least one processor, an electronic design and extracting hierarchical crossing path exception information from a hierarchical design view associated with the electronic design. Embodiments may further include transferring the hierarchical crossing path exception information to a block view associated with the electronic design and…
Simulation event reduction and power control during MBIST through clock tree management
Granted: September 22, 2020
Patent Number:
10783299
An exemplary system, method, and computer-accessible medium may be provided, which may include, for example, receiving a design a memory including a plurality MBIST logic paths and a plurality of non-MBIST logic paths, determining particular non-MBIST logic path(s) of the non-MBIST logic paths to deactivate, and deactivating only the particular non-MBIST logic path(s). The particular non-MBIST logic path(s) may be deactivated using a clock signal. A simulation on the memory may be…
Systems and methods for performing a reset sequence simulation in an electronic design
Granted: September 22, 2020
Patent Number:
10783283
The present disclosure relates to a computer-implemented method for performing a reset sequence simulation in an electronic design. The method may include receiving, using at least one processor, a sequence file including at least one reset, input and cycle value. The method may further include sampling during a first set of cycles set forth in the sequence file and detecting stability at a time point during a first set of cycles. The method may also include bypassing sampling during one…
System, method, and computer program product for clock gating in a formal verification
Granted: September 22, 2020
Patent Number:
10782767
The present disclosure relates to a method for reducing power consumption. Embodiments include providing an electronic design of a device under test having a plurality of flip-flops associated therewith. Embodiments also include selecting a first set of flip-flops from the plurality of flip-flops and disabling a first clock associated with the first set of flip-flops without changing a value of the first set of flip-flops. Embodiments may further include selecting a second set of…
Infinite-depth path-based analysis of operational timing for circuit design
Granted: September 15, 2020
Patent Number:
10776547
A static timing analysis system for finding timing violations in a digital circuit design prior to circuit fabrication, and associated methods, use infinite-depth path-based analysis (IPBA) to achieve reduced pessimism as opposed to systems or methods employing only graph-based analysis (GBA), but with greatly reduced compute time requirements, or greater logic path coverage, versus systems or methods employing conventional or exhaustive path-based analysis. IPBA achieves the improved…
