System and method for memory control having selectively distributed power-on processing
Granted: July 21, 2020
Patent Number:
10719058
A system and method are provided for memory control, having selectively distributed power-on processing. A memory controller executes responsive to a master control operation to actuate a plurality of operational tasks on a memory device. The memory controller includes a first power-on block executable to actuate one or both of initialization and training operations corresponding to the memory device. A PHY portion coupled to the memory controller portion executes to adaptively configure…
Circuit design routing using multi-panel track assignment
Granted: July 7, 2020
Patent Number:
10706201
Various embodiments provide for circuit design routing using a track assignment based on a plurality of panels (also referred to herein as a multi-panel track assignment). According to some embodiments, a track assignment of a wire within a particular panel is performed based on a primary panel bound or limit and a secondary panel bound or limit. For instance, during a track assignment for a particular wire falling within a particular panel, an embodiment can first attempt to assign the…
Testing for memories during mission mode self-test
Granted: July 7, 2020
Patent Number:
10706952
Systems and methods disclosed herein provide for efficiently testing memories during mission mode self-test (“MMST”) without destroying any original functional data. Embodiments provide for a converter to feed a manipulated version of the original functional data back into the tested memories. Embodiments further provide an accumulator to count the occurrences of correctable and uncorrectable errors associated with the tested memories.
Testing for memory error correction code logic
Granted: July 7, 2020
Patent Number:
10706950
Systems and methods disclosed herein provide for improved testing of memory error correction code (“ECC”) logic with memory built-in self-test (“MBIST”). Embodiments provide for a masking element to inject one or more faults into the ECC logic during at least one of a manufacturing test (“MFGT”) and a power-on-self-test (“POST”), wherein, based on the injected faults, it can be determined if the ECC logic contains any errors.
Methods for layout driven synthesis of transmission line routes in integrated circuits
Granted: July 7, 2020
Patent Number:
10706206
A computer may generate a record of a template associated with a schematic design corresponding to an integrated circuit design. The template may have one or more instances corresponding to one or more initial parameters associated with a chain of one or more transmission line components of the integrated circuit design. The computer may then modify content of the chain of one or more transmission line components in a circuit layout corresponding to the schematic design within the…
Devices and methods for balanced routing tree structures
Granted: July 7, 2020
Patent Number:
10706202
Systems, methods, media, and other such embodiments described herein relate to generation of routing trees. One embodiment involves accessing a circuit design with a source and a plurality of sinks, and then using a first bottom-up wavefront analysis to select branch point candidates for the sinks. A branch point cost function is used to select among the branch point candidates. This process may be repeated until a final tier of analysis results in a final wavefront that is within a…
Graphical user interface for interactive macro-cell placement
Granted: July 7, 2020
Patent Number:
10706199
Aspects of the present disclosure address systems, methods, and an improved graphical user interface (GUI) for providing interactive macro-cell placement for integrated circuit (IC) design. The method includes causing display of a GUI that includes a display of an IC floor plan comprising multiple macro-cells, The method further includes receiving a user selection of two or more macro-cells from the IC floor plan, and updating the GUI to display layout options for the two or more…
System, method, and computer program product for over-constraint/deadcode detection in a formal verification
Granted: July 7, 2020
Patent Number:
10706195
The present disclosure relates to a method for use in the formal verification of an electronic circuit. Embodiments may include receiving, using a processor, a portion of an electronic circuit design and analyzing a syntactic structure of a string associated with the electronic circuit design. Embodiments may also include generating a parse tree, based upon, at least in part, the analysis and traversing the parse tree to identify one or more conditional nodes. Embodiments may further…
High-speed low VT drift receiver
Granted: July 7, 2020
Patent Number:
10705984
Embodiments relate to systems, methods, and computer-readable media to enable design and creation of receiver circuitry. One embodiment is a receiver apparatus comprising a plurality of receiver arrangements, each receiver arrangement having a sampling circuit and a multi-stage differential amplifier connected to the sampling circuit. Each receiver arrangement is configurable via switches between an amplifying mode and an autozero mode. Control circuitry may select output data from a…
Method and system for generating a validation test
Granted: June 30, 2020
Patent Number:
10698802
A method for generating a validation test for testing an electronic design may include using a processor, analyzing a plurality of actions of a validated scenario to identify an executable corresponding to each of the actions and to identify one or a plurality of variables referred to by each of the actions; using a processor, identifying actions in said plurality of actions that correspond to different executables of the identified executables but refer to a same variable of said one or…
Method and system for profiling performance of a system on chip
Granted: June 30, 2020
Patent Number:
10698805
A method for debugging a system on chip (SoC) under test, may include automatically inserting commands in a test code for testing the SoC for invoking printing of messages of data, each message of the messages including start time, end time of each executed action of a plurality of actions, the executed action to be invoked by the test code when testing the SoC, the data further including identity of a processing component of a plurality of processing components of the SoC, on which the…
Method and system for performing cross-validation for model-based layout recommendations
Granted: June 30, 2020
Patent Number:
10699051
Disclosed are method(s), system(s), and article(s) of manufacture for implementing layouts for an electronic design using machine learning, where users re-use patterns of layouts that have been previously implemented, and those previous patterns are applied to create recommendations in new situations. An improved approach to perform cross-validations is provided.
System, method and computer-accessible medium for automated identification of embedded physical memories using shared test bus access in intellectual property cores
Granted: June 30, 2020
Patent Number:
10699795
A method for identifying a physical memory(ies) associated with a logical memory(ies) in a memory design can include (a) receiving a generic netlist for the memory design, (b) generating a test mode for the memory using the generic netlist, (c) determining the logical memory(ies); (d) performing a simulation on the test mode for the logical memory(ies); and (e) identifying the physical memory(ies) by tracing chip selects for the physical memory(ies) to the logical memory(ies). The…
Process for analyzing printed circuit board and packaging manufacturing design rules
Granted: June 23, 2020
Patent Number:
10691868
The present disclosure relates to a system and method for use in an electronic circuit design. Embodiments may include an electronic computer aided design (“CAD”) system configured to receive one or more design rules and to receive one or more manufacturing rules. The CAD system may be further configured to analyze design database objects from the electronic design with respect to the manufacturing rules. The CAD system may generate a manufacturing output file, based upon, at least…
System, method, and computer program product for displaying bump layout for manufacturing variations
Granted: June 16, 2020
Patent Number:
10685167
The present disclosure relates to a computer-implemented method for use in design for manufacturing associated with a die or package. Embodiments may include providing, using a processor, an electronic design and displaying, at a graphical user interface, at least a portion of a layout associated with the electronic design. Embodiments may also include determining an expected thermal or centrifuge force manufacturing variation associated with the electronic design. Embodiments may…
Methods, systems, and computer program products for implementing an electronic design with physical simulation using layout artwork
Granted: June 16, 2020
Patent Number:
10685166
Various techniques implement an electronic design with physical simulations using layout artwork. The approximate behaviors of the electronic design are determined. A region in the electronic design is identified. A first three-dimensional model is identified, if pre-existing, or generated, if non-existing, for the region in the electronic design. The behaviors of the region is determined using at least physics-based techniques or methodologies that are preconditioned upon at least a…
Circuit design routing based on parallel run length rules
Granted: June 16, 2020
Patent Number:
10685164
Various embodiments provide for circuit design routing based on parallel run length (PRL) rules. In particular, a plurality of PRL rules is accessed and used to generate a set of additional routing blockages around an existing routing blockage of the circuit design. The additional routing blockages can be positioned relative to the existing routing blockage. During routing, the set of additional routing blockages can be modeled into a capacity map, which is then used by global to…
Methods for performing Boolean operations on planar region boundaries defined by parametric curves
Granted: June 9, 2020
Patent Number:
10678986
A method includes receiving a first list including a plurality of first curves defining a first boundary set and a second list including a plurality of second curves defining a second boundary set. The first and second curves are indicative of features in an integrated circuit based on parametric values. The method includes determining intersections between pairs of curves from the first and the second lists, assigning a node to each intersection point of a pair of curves, and…
Methods, systems, and computer program product for binding and back annotating an electronic design with a schematic driven extracted view
Granted: June 9, 2020
Patent Number:
10678978
Disclosed are methods, systems, and articles of manufacture for binding and annotating an electronic design with a schematic driven extracted view. These techniques identify a schematic design and an extracted view of an electronic design and bind the schematic design with the extracted view. The resulting binding information concerning binding the schematic design with the extracted view is stored in a data structure. The schematic design may be annotated with extracted view information…
Editing of layout designs for fixing DRC violations
Granted: June 2, 2020
Patent Number:
10671793
The present embodiments relate to providing an overlap view of external and internal components of all instance circuit cells related to a master circuit cell in a same layout view. A layout of a circuit having a plurality of instance circuit cells of a master circuit cell is provided. Further, a graphical user interface including a user selectable option for an overlay view is provided. In addition, responsive to the selection of the overlay view, the plurality of instance circuit cells…
