Circuits and methods for reducing asymmetric aging effects of devices
Granted: May 26, 2020
Patent Number:
10666242
A delay line can include a number of delay elements connected in series, each selected to impart an overall delay to an input signal. The delay line can include delay selection logic to select a subset of the delay elements to delay the input signal. The delay line can include delay element enable logic to enable the selected subset of the delay elements to delay the input signal. Further, the remaining delay elements can be disabled from contributing any delay to the input signal, and a…
Route generation and buffer placement for disjointed power domains in an integrated circuit
Granted: May 19, 2020
Patent Number:
10657302
The present embodiments relate to buffering signals between disjointed power domains with similar power profiles in an integrated circuit. According to some aspects, embodiments relate to a method in which an electronic design automation (EDA) tool displays a schematic including a plurality of first power domains having a first power profile and a plurality of second power domains having a second power profile. The EDA tool generates graph including a plurality of points and a plurality…
System and method for visualizing event sequences for expressions using both hardware and software state information
Granted: May 12, 2020
Patent Number:
10650174
The present disclosure relates to a system and method for use in an electronic design environment. Embodiments may include receiving, using at least one processor, an electronic design and generating a unique name for each hardware state element associated with the electronic design. Embodiments may further include generating a unique name for each software state element associated with the electronic design. Embodiments may also include combining a plurality of unique names into an…
Memory command interleaving
Granted: May 5, 2020
Patent Number:
10642684
Various embodiments described herein provide for grouping read-modify-writes (RMWs) such that multiple RMW command sequences can be executed (or rearranged in the command queue) in an interleaved manner rather than being executed in order. In particular, various embodiments described herein split the read and write components (commands) of multiple RMW command sequences, group the read components in the command queue to execute consecutively, and group the write components in the command…
System and method to estimate a number of layers needed for routing a multi-die package
Granted: May 5, 2020
Patent Number:
10643020
Embodiments included herein are directed towards a system and method for implementing an IC package design with an IC package design estimator. Embodiments may include estimating a number of layers for an integrated circuit (IC) package design that includes a plurality of IC die designs. Embodiments may further include determining whether the estimated number of layers can accommodate routing demands for interconnections between the IC package design and each of the plurality of IC die…
View pruning for routing tree optimization
Granted: May 5, 2020
Patent Number:
10643019
Electronic design automation systems, methods, and media are presented for view pruning to increase the efficiency of computing operations for analyzing and updating a circuit design for an integrated circuit. One embodiment involves accessing a circuit design stored in memory that is associated with a plurality of views, selecting a first view of the plurality of view for view pruning analysis, and identifying a plurality of input values for the first view of the plurality of views.…
System and method for determining return path quality in an electrical circuit
Granted: May 5, 2020
Patent Number:
10643018
Embodiments include herein are directed towards a method for electronic circuit design and more specifically towards determining return path quality in an electrical circuit. Embodiments may include providing, using a processor, an electronic circuit design and identifying at least one net associated with the electronic circuit design. Embodiments may further include extracting an ideal loop inductance for the at least one net and extracting a real loop inductance for the at least one…
System, method and computer program product for design rule awareness associated with die and package electronic circuit co-design
Granted: May 5, 2020
Patent Number:
10643016
The present disclosure relates to a computer-implemented method for electronic circuit design awareness. Embodiments may include providing, using a processor, an electronic design having a package layout and a die layout associated therewith. Embodiments may also include displaying at a graphical user interface, the package layout and allowing, at the graphical user interface, a user to edit the package layout. Embodiments may further include determining, using the processor, an impact…
Irregular sink arrangement for balanced routing tree structures
Granted: May 5, 2020
Patent Number:
10643014
Systems, methods, media, and other such embodiments described herein relate to generation of routing trees. One embodiment involves accessing a circuit design comprising an irregular sink arrangement. Different grid templates may be identified for assisting with balanced routings at different levels of a routing tree to connect the sinks of the circuit design. As part of such operations, costs for different routings using the different grid templates are calculated and compared. A lowest…
Automatic design and verification of safety critical electronic systems
Granted: May 5, 2020
Patent Number:
10643011
Devices, methods, computer readable media, and other embodiments are described for design and verification of safety critical electronic systems. Some embodiments integrate functional safety (FS) data with circuit design data for use in electronic design automation (EDA) operations. One embodiment involves a device accessing FS and circuit design data; automatically analyzing register transfer level (RTL) design data using the FS data to perform one or more FS quality checks; and placing…
Multi-channel memory interface
Granted: May 5, 2020
Patent Number:
10642538
Various embodiments provide for a multi-channel memory interface capable of supporting a multi-channel memory module (e.g., DIMM) that combines different memory types, such as DDR4/DDR5, DDR5/LPDDR5, or LPDDR4/LPDDR5, through a single physical layer (PHY) interface.
System and method for electrically and spatially aware parasitic extraction
Granted: April 28, 2020
Patent Number:
10635848
The present disclosure relates to a computer-implemented method for parasitic extraction. The method may include providing, using one or more processors, an electronic design having IP and/or metal fill content associated therewith. The method may further include identifying at least one layer associated with the content to be modeled and identifying at least one layer associated with the content to be ignored. The method may also include discarding one or more shapes associated with the…
Methods, systems, and computer program products for implementing an electronic design with hybrid analysis techniques
Granted: April 28, 2020
Patent Number:
10635770
Various techniques implement an electronic design with hybrid analysis techniques. An activity map is identified or generated for an electronic design. The electronic design is reduced into a reduced electronic design at least by applying a plurality of reduction processes to different portions of the electronic design based in part or in whole upon the activity map. Transient behaviors of the electronic design may be determined or predicted at least by performing one or more transient…
System, method, and computer program product for displaying multiple traces while debugging during a formal verification
Granted: April 28, 2020
Patent Number:
10635768
The present disclosure relates to a method for electronic design. Embodiments may include receiving, using a processor, an electronic design and performing formal verification upon at least a portion of the electronic design for a specific problem statement. Embodiments may further include generating a plurality of traces associated with the formal verification satisfying the specific problem statement and displaying, at a graphical user interface, an option to select at least one of the…
System and method for simulating channels using true strobe timing
Granted: April 21, 2020
Patent Number:
10628624
Embodiments included herein may be used for characterizing and analyzing an electronic system design including a parallel interface. Embodiments may include identifying an electronic design including a design of a parallel interface. Embodiments may also include determining a single circuit representation including the design of the parallel interface from the electronic design. Embodiments may further include analyzing the single circuit representation at a channel analysis module…
Method and system for automatically extracting layout design patterns for custom layout design reuse through interactive recommendations
Granted: April 21, 2020
Patent Number:
10628546
Disclosed are method(s), system(s), and article(s) of manufacture for implementing layouts for an electronic design using machine learning, where users re-use patterns of layouts that have been previously implemented, and those previous patterns are applied to create recommendations in new situations.
Checking minimum width, minimum distance and maximum curvature of planar region boundaries defined by arbitrary parametric curves
Granted: April 21, 2020
Patent Number:
10627713
A method for determining a minimum width, a minimum distance and maximum curvature violations for an integrated circuit (IC) design is provided. The method includes creating a set of offset boundary curves based on inputs received for a given boundary set and a defined minimum width and a defined minimum distance. The method also includes determining all intersections between all pairs of offset boundary curves and assigning a node to each intersection point. The method also includes…
Error-controlled discretization of parametric curves for integrated circuit design and manufacture
Granted: April 14, 2020
Patent Number:
10620531
A method including receiving a parametrized curve indicative of a feature in an integrated circuit is provided. The method includes selecting a first parameter value associated with a first point in the parametrized curve, determining a pre-selected number of derivative values in a Taylor series for the parametrized curve at the first point, and determining a second parameter value for a second point in the parametrized curve based on the pre-selected number of derivative values. The…
Method of bias temperature instability calculation and prediction for MOSFET and FinFET
Granted: April 14, 2020
Patent Number:
10621386
A method, a system and a non-transitory machine-readable storage medium are provided. In one or more aspects, a computer-implemented method for bias temperature instability (BTI) calculation of a device includes simulating the device, using an electronic design automation tool. The simulation includes determining a first degradation value after applying a first sequence of stress values to the device for a first plurality of time steps. The simulation further includes determining a first…
Algorithmic modeling interface process
Granted: April 14, 2020
Patent Number:
10620802
The present disclosure relates to a system and method for algorithmic modeling interface (“AMI”) model development. Embodiments may include enabling a selection from a plurality of templates associated with an advanced equalization algorithm at a graphical user interface. Embodiments may further include receiving a selection of at least one of the plurality of templates at the graphical user interface and displaying a selected template at the graphical user interface. Embodiments may…
