Content addressable memory in an emulation system
Granted: December 26, 2017
Patent Number:
9852807
Disclosed herein are components of an emulation system capable of efficiently recreating the functionality a CAM/TCAM memory circuit. Rather than using specialized gates or the existing processors, the embodiments described herein configure/instruct the existing memory circuits of the emulation system to imitate a search engine function that queries the existing RAM circuits, portions of which are reconfigured to function as CAM/TCAM memory. The hardware-based search engine and the…
Method and system for implementing a requirements driven closed loop verification cockpit for analog circuits
Granted: December 26, 2017
Patent Number:
9852258
Disclosed is an approach to implement a requirements-driven analog verification flow. Disparate islands of verification tasks are performed with individual cellviews to be set into an overarching and closed loop verification flow context for a project or a complex verification task.
Method and system for automated debugging memory allocation and memory release
Granted: December 26, 2017
Patent Number:
9852046
A method and system for debugging memory allocation and memory release may include recording execution events of an execution run of a program including data related to objects pertaining to that program, and data related to object association pertaining to that program at a plurality of points in time. The method may also include receiving via a user interface a user selection of an object of said objects. The method may further include identifying one or a plurality of pointers…
Methods and systems for enabling concurrent editing of electronic circuit layouts
Granted: December 12, 2017
Patent Number:
9842183
Methods and systems of an electronic circuit design system described herein provide a new layout editor tool to make edits in an electronic circuit layout. A plurality of partitions is created in the electronic circuit layout. The new layout editor tool enables multiple electronic circuit designers to edit a different partition of the plurality of partitions of the same electronic circuit layout at the same time and save the edited partition locally.
Systems and methods for binding mismatched schematic and layout design hierarchy
Granted: December 12, 2017
Patent Number:
9842178
Disclosed herein are systems and methods that allow a layout editor function, presented in a graphical user interface, of an EDA, to indicate certain layout instances or “cell views” as “transparent.” The instances are indicated as transparent using various layout editor commands or layout designer markers. Unlike conventional solutions, a binder within the layout editor of the EDA is not required to bind layout transparent instances to corresponding instances in a related…
Behavioral modeling of jitter due to power supply noise for input/output buffers
Granted: December 12, 2017
Patent Number:
9842177
Aspects of the present disclosure involve a system comprising a computer-readable storage medium storing at least one program, and a method for behavioral modeling of jitters due to power supply noise for input/output (I/O) buffers. The method may include accessing physical model data describing a physical structure of an integrated circuit device, and accessing a behavioral model schema for evaluating electrical characteristics of the integrated circuit device including jitter effects…
Efficient extraction of the worst sample in Monte Carlo simulation
Granted: December 5, 2017
Patent Number:
9836564
A system, method, and computer program product for reducing the number of Monte Carlo simulation samples required to determine if a design meets design specifications. The worst sample for each specification acts as a design corner to substitute for a full design verification. Embodiments determine the maximum number of samples needed, perform an initial performance modeling using an initial set of samples, and estimate the failure probability of each of the remaining samples based on…
Tunable impedance circuit for a transmitter output stage
Granted: November 28, 2017
Patent Number:
9831874
A system, a method and circuit arrangements for adjusting an output impedance of an electric circuit involve impedance cells connected to an output terminal in parallel with one another. Each impedance cell includes parallel branches. Each branch includes switching units and resistors. The resistors in a branch are connected in series and contribute to an overall impedance of their corresponding impedance cell. Each switching unit is configurable to selectively bypass a corresponding one…
Methods and systems for generation and editing of parameterized figure group
Granted: November 28, 2017
Patent Number:
9830417
An electronic circuit design system for generating a programmable set of figures of an electronic circuit layout is provided. The system includes a non-transitory machine-readable layout database storing an electronic circuit layout of an electronic circuit design. The system further includes a circuit designer interface for viewing representations of the electronic circuit layout on a display unit and receiving inputs by one or more electronic circuit designers. The system further…
Method and system of evaluation of validity of a refinement rule for a hardware emulation
Granted: November 21, 2017
Patent Number:
9824175
A method for automatically verifying validity of application of a refinement rule includes calculating a set of values that characterize a hierarchy of elements of the emulation. A currently calculated value for a first element at a first level of the hierarchy is compared with a previously calculated value that characterized the first element at a previous time. If the currently calculated value is the same as the previously calculated value, application of the refinement rule is…
Method and system for generating post-silicon validation tests
Granted: November 21, 2017
Patent Number:
9823305
A method for generating a post-silicon validation test for a system on chip (SOC), may include obtaining a selection of action scenarios from a set of scenarios originally constructed for generating simulation tests; combining the selected scenarios into a combined scenario in which the selected scenarios are to be executed in parallel; and generating a post-silicon test code corresponding to the combined scenario.
Method of adaptively controlling the pre-cursor coefficient in a transmit equalizer
Granted: November 14, 2017
Patent Number:
9819520
A circuit and method for controlling a pre-cursor coefficient in an equalizer of a transmitter device. An input signal from the transmitter is converted into a data signal that includes data symbols transmitted in successive unit intervals. An error signal is formed by comparing the input signal to a threshold value. A determination is made whether to adjust the pre-cursor coefficient, by correlating a sample of the error signal with samples of the data signal from one unit interval…
Methods, systems, and articles of manufacture for implementing high current carrying interconnects in electronic designs
Granted: November 14, 2017
Patent Number:
9817941
Various embodiments implement additional connectivity for electronic designs by identifying one or more regions for a route in normal connectivity of an electronic design, identifying a plurality of seeding segments from the route based at least in part upon the one or more regions, identifying a plurality of additional nodes in the plurality of seeding segments, and generating one or more additional routes connecting the plurality of additional nodes in the plurality of seeding…
Method, system, and computer program product for verifying an electronic circuit design with a graph-based proof flow
Granted: November 14, 2017
Patent Number:
9817930
Various mechanisms identify an electronic design model and determine a data propagation diagram by receiving a set of path property sources or destinations, determine a set of helper properties for the data propagation diagram by traversing at least a portion of the data propagation diagram, and verify the electronic design model by examining one or more helper properties and determining verification of the one or more helper properties leads to concrete results to generate verification…
Method and system for construction of a highly efficient and predictable sequential test decompression logic
Granted: November 14, 2017
Patent Number:
9817069
Systems and methods for a sequential decompressor which builds equations predictably provide a first-in, first out (“FIFO”) shift register which is fed by a first XOR decompressor and provides outputs to a second XOR decompressor.
Method and system for improving efficiency of sequential test compression using overscan
Granted: November 14, 2017
Patent Number:
9817068
Systems and methods efficiently bring additional variables into a Pseudo-Random Pattern Generator (“PRPG”) in the early cycles of an automatic test pattern generation (“ATPG”) process without utilizing any additional hardware or control pins. Overscanning (e.g., scanning longer than the length of the longest channel) for some additional cycles brings in enough variables into the PRPG. Data corresponding to earlier cycles of the ATPG process is removed.
System and method for reliable high-speed data transfer in multiple data rate nonvolatile memory
Granted: November 7, 2017
Patent Number:
9811273
The subject system and method are generally directed to ensuring reliable high speed data transfer in multiple data rate nonvolatile memory, such as double data rate (DDR) nonvolatile NAND flash memory and the like. The system and method provide measures to achieve read and write training for data signals (DQ) and the data strobe signal (DQS), one relative to the other. In such manner, high speed data transfers to and from nonvolatile memory such as flash devices may be performed with a…
Efficient extraction of K-sigma corners from Monte Carlo simulation
Granted: October 31, 2017
Patent Number:
9805158
A system, method, and computer program product for efficiently finding the best Monte Carlo simulation samples for use as design corners for all design specifications to substitute for a full circuit design verification. Embodiments calculate a corner target value matching an input variation level by modeling the circuit performance with verified accuracy, estimate the corner based on a response surface model such that the corner has the highest probability density (or extrapolation from…
Method and apparatus for Laplace transform system simulation
Granted: October 31, 2017
Patent Number:
9805151
Disclosed are methods and apparatus for implementing system simulation. The method includes generating a high-order equation based on a transfer function that represents characteristics of at least one frequency-domain component in a circuit; converting the high-order equation into a state equation comprising a series of state variables, wherein the high-order equation and the state equation have corresponding coefficients for each order and state variable, and the coefficients of the…
Methods, systems, and computer program product for implementing a simulation platform with dynamic device model libraries for electronic designs
Granted: October 24, 2017
Patent Number:
9798840
Various embodiments are to a simulation platform with dynamic device model libraries and the implementation therefor. The simulation platform includes one or more servers hosting thereupon a database management system, a simulation frontend, and a simulation backend. The simulation frontend includes or is operatively coupled to one or more electronic design databases managed by a database management system, stored in a persistent storage device, and including design data in one or more…
