System for concurrent target diagnostics field
Granted: February 27, 2018
Patent Number:
9904759
A system for concurrent target diagnostics is disclosed. The system comprises dedicated FPGA for generating test data to test target connections between an emulator and a target system. In this way, domains of the emulator may continue to emulate at least a portion of a hardware design during the testing of the target connections. Further, a multiplexer operable to select target connections for testing eliminates errors resulting from manual swapping of target connections during the…
Methods, systems, and computer program product for implementing DRC clean multi-patterning process nodes with lateral fills in electronic designs
Granted: February 27, 2018
Patent Number:
9904756
Disclosed are techniques for implementing DRC clean multi-patterning process nodes with lateral fills. These techniques identify design rules governing multi-patterning and track patterns by accessing a rule deck to retrieve the design rules, identify a first shape and a second shape sandwiching a space and characteristics of the first and second shapes by examining design data of the electronic design, insert one or more lateral fill shapes in the space by implementing the one or more…
Method and system for automatically identifying test runs contributing to coverage events of interest in verification test data
Granted: February 13, 2018
Patent Number:
9891281
A method includes receiving from a user, via a user interface, coverage-event characteristics. Using a processor, output data of test runs executed on a device-under-test is analyzed to identify one or a plurality of coverage events that possess the coverage-event characteristics and to identify one or a plurality of contributing test runs in said test runs that contributed to said one or a plurality of coverage events. Information on said one or a plurality of contributing test runs is…
System and method for using heterogeneous hierarchical configurations for electronic design reuse
Granted: February 6, 2018
Patent Number:
9886538
The present disclosure relates to a computer-implemented method for electronic design configuration reuse. The process may include providing an electronic design having one or more mixed signal configurations. The process may further include storing at least one digital configuration and at least one analog configuration at an electronic design database. The process may further include allowing the one or more mixed signal configurations to access the at least one digital configuration…
Universal shifter and rotator and methods for implementing a universal shifter and rotator
Granted: January 30, 2018
Patent Number:
9880810
A single block shifter design performing arithmetic and logical shift operations on input operands of multiple types is disclosed. The shifter design may be configurable and automatically generated to support multiple partition types including at least one of 80-bit, 40-bit, and 20-bit partition type. The shifter may also be configured and automatically generated to perform rotate operations on input operands. The shifter may include two stages where the first stage includes multiple…
Systems and methods for partitioned root search for error locator polynomial functions in reed-solomon forward error correction decoding
Granted: January 30, 2018
Patent Number:
9882585
Aspects of the present disclosure involve a system comprising a computer-readable storage medium storing at least one program, and a method of improving a speed of decoding digital data. The method may include receiving a digital communication that includes digital data; specifying a partition of a plurality of elements of a Galois field into a plurality of sets; specifying an error locator polynomial function for a Reed-Solomon forward error correction module; specifying, for each set…
Per-group delay line architecture to de-skew input/output timing between a high bandwidth memory (HBM) physical (PHY) interface and the HBM device
Granted: January 30, 2018
Patent Number:
9881664
A method for minimizing skew in a High Bandwidth Memory (HBM) device is provided. The method includes grouping a plurality of information bits of the HBM device into at least two groups of information bits, wherein the plurality of information bits includes a plurality of data bits and a plurality of control bits, and the plurality of information bits are grouped such that each group of the at least two groups includes at least one control bit and the at least two groups form a byte of…
Method and system for timing analysis with adaptive timing window optimization for determining signal integrity impact
Granted: January 30, 2018
Patent Number:
9881123
A method and system are provided for timing analysis of an electronic circuit design. A timing graph defines a plurality of timing paths through different subsections of the electronic circuit design. A timing window is defined for each of the nodes included in a timing path. At least one preliminary round of a predetermined signal integrity analysis is executed on the circuit design based on the timing windows to identify at least one pair of crosstalk-coupled victim and aggressor…
Method, system, and computer program product for implementing a multi-fabric mixed-signal design spanning across multiple design fabrics with electrical and thermal analysis awareness
Granted: January 30, 2018
Patent Number:
9881120
Various embodiments implementing a multi-fabric mixed-signal electronic system design spanning across multiple design fabrics with electrical and/or thermal analysis awareness. A schematic design may be extracted from and a power delivery network (PDN) model may be determined from a plurality of layouts in multiple design fabrics in a multi-fabric design environment platform. A PDN-aware, multi-fabric full system schematic may be constructed by assembling the PDN model and the schematic…
Methods, systems, and computer program product for constructing a simulation schematic of an electronic design across multiple design fabrics
Granted: January 30, 2018
Patent Number:
9881119
Disclosed are techniques for generating a parasitic-aware simulation schematic across multiple design fabrics. These techniques identify a first extracted model from existing extracted models for a first circuit component design in a first layout in a first design fabric of an electronic design that spans across multiple design fabrics. These techniques further generate a simulation schematic by inserting the first extracted model into the simulation schematic. In addition, a simulation…
Method and system for efficient data streaming in an emulation system
Granted: January 23, 2018
Patent Number:
9876729
An emulation system for efficient data streaming is provided. The emulation system comprises a first device configured to product machine readable binary data, and a second device configured to receive the data. The emulation system further comprises a centralized first-in first-out (FIFO) memory unit. The centralized FIFO memory unit interfaces between the first device and the second device. The centralized FIFO memory unit is configured to receive the data from the first device, and…
Comprehensive path based analysis process
Granted: January 23, 2018
Patent Number:
9875333
The present disclosure relates to a system and method for electronic design automation. Embodiments may include receiving, using at least one processor, an electronic design and determining one or more graph based analysis (“GBA”) violating nodes associated with the electronic design. Embodiments may include identifying a non-covered violating node from the GBA violating nodes and determining a worst timing path through the non-covered violating node. Embodiments may further include…
Method and system for import of mask layout data to a target system
Granted: January 23, 2018
Patent Number:
9875329
A host system for transferring data to a target system is provided. The host system may include a layout database for storing mask layout data representing an integrated circuit (IC) in terms of planar geometric shapes. The hosts system may further include a processor configured to import the mask layout data from the layout database to a memory-mapped disk in the host system. The processor is further configured to translate the mask layout data into one or more cell views according to a…
Method and apparatus for testing error correction code (ECC) logic and physical memory onboard a manufactured integrated circuit (IC)
Granted: January 9, 2018
Patent Number:
9865362
Method and apparatus for testing the memory components of an integrated Circuit (IC) using a routing logic and a built-in design for test (DFT) hardware processing device. Based on input provided from an interface controller to the IC, the IC is tested according to one of at least two modes. In a first mode, the built-in DFT hardware processing device executes a test that checks for faults in the physical memory of the IC. In a second mode, the built-in DFT hardware processing device…
System and method for modeling electronic circuit designs
Granted: January 9, 2018
Patent Number:
9864827
The present disclosure relates to a system and method for modeling an electronic circuit design. Embodiments may include receiving, at one or more computing devices, an electronic circuit design. Embodiments may also include partitioning, at a graphical user interface configured to display at least a portion of the electronic circuit design, at least one portion of the electronic circuit design into one or more sub-zones and generating, at the graphical user interface, one or more ports…
System and method for diagnosing failure locations in electronic circuits
Granted: January 9, 2018
Patent Number:
9864004
Embodiments for diagnosing failure locations in one or more electronic circuits. Embodiments may include generating a plurality of core instances of at least one core, for each electronic circuit, with one or more outputs and compressing the outputs of each instance into primary output pins based upon compression equations. Embodiments may include applying test patterns to the plurality of core instances and identifying failures based upon compressed test patterns received at the primary…
Method and system for generating post-silicon validation tests
Granted: January 2, 2018
Patent Number:
9858371
A method for generating a minimized combined scenario for use in simulation, from a post-silicon validation test that includes a combined scenario, may include obtaining a failed scenario loop of a scenario of the combined scenario that includes combined action scenarios that were executed in loops during a post-silicon validation test of a system on chip; and adding any loops of other scenarios of the combined scenario that were executed at least partially concurrently with the failed…
Interpolating feedback divider
Granted: January 2, 2018
Patent Number:
9859904
Systems and methods disclosed herein provide for a fractional feedback divider with reduced jitter at the output without increasing the input clock frequency and with minimal power increase. Embodiments of the system provide for interpolating, with a multiplexer, different output clock signals depending on whether an extra half period of resolution from the input clock is needed for a certain output clock cycle.
Method and system for displaying waveform results directly on a schematic
Granted: January 2, 2018
Patent Number:
9858374
An improved approach is provided to displaying waveform data, where a schematic and corresponding waveform data can be displayed directly on a schematic of an electronic circuit. By providing both the schematic and waveform results in a same display, circuit designers and verification engineers are given more control over their working environments and can more efficiently utilize available data including the schematic and the waveform data. Furthermore, results can be pinned to a…
Methods, systems, and computer program product for verifying an electronic design
Granted: January 2, 2018
Patent Number:
9858372
Disclosed are techniques for implementing formal verification of an electronic design. These techniques identify a target property for verification in a hierarchical electronic design that has a plurality of hierarchies and perform hierarchical synthesis on a hierarchy or a portion thereof in the plurality of hierarchies while black-boxing a remaining portion of the hierarchical electronic design. Cone of influence (COI) data that is relevant to the target property may be determined at…
