Method and system for improving efficiency of XOR-based test compression using an embedded serializer-deserializer
Granted: March 28, 2017
Patent Number:
9606179
Systems and methods disclosed herein provide for generating extra variables for an ATPG system utilizing compressed test patterns in the event an ATPG process is presented with faults requiring a higher number of care-bits than can be supported efficiently by the current hardware. The systems and methods provide for a multi-stage decompressor network system with an embedded serializer-deserializer. The systems and methods use a XOR decompressor in a first stage and a…
Method and system to perform equivalency checks
Granted: March 14, 2017
Patent Number:
9594861
An improved approach is provided to implement equivalency checking. A check is performed as to whether two designs are equivalent without needing to analyze their outputs on a cycle-by-cycle basis. Instead, the two designs are checked to see if they are equivalent on the transaction-level. This approach abstracts the timing delays between the two designs, which allows verification of data transportation and transformation between the designs.
Methods, systems, and articles of manufacture for implementing scalable statistical library characterization for electronic designs
Granted: March 14, 2017
Patent Number:
9594858
Various embodiments scalable statistical library characterization for electronic designs by identifying an electronic design, performing circuit simulations on strongly connected components on a component-by-component basis, performing the logic cone analysis on the entire electronic design, and performing combinations of influences on the electronic design caused by variations of parameters. Some embodiments perform simulations on one or more stronger parameters or the strongest…
Methods and devices for a DDR memory driver using a voltage translation capacitor
Granted: March 7, 2017
Patent Number:
9589627
Embodiments relate to systems, methods and computer readable media to enable design and creation of memory driver circuitry using a voltage translation capacitor. One embodiment is high speed level translation memory driver apparatus comprising a plurality of field effect transistors (FETs), complementary metal oxide semiconductor (CMOS) logic gates to drive the FETs, and a voltage translation capacitor with a first terminal of the voltage translation capacitor connected to an output of…
Method and apparatus for integrating spice-based timing using sign-off path-based analysis
Granted: March 7, 2017
Patent Number:
9589096
Methods and systems provide setup and generation of SPICE results for a set of timing path(s) and integration of SPICE simulation with static timing analysis (STA) path-based results generation. In an embodiment, a method may select a candidate set of timing paths, perform path based analysis (PBA) on the selected paths, generate SPICE results for the selected paths, and render the PBA and SPICE results in an integrated user interface to facilitate sign off based on annotated constraints…
Systems and methods for viewing analog simulation check violations in an electronic design automation framework
Granted: March 7, 2017
Patent Number:
9589085
A system, method, and computer program product for viewing analog simulation check violations in an EDA framework. Embodiments combine input data tables into a single data table for each check type using SQL inner join operations, create a SQL view of the single data table to list individual check violations, and output the view for user inspection of the corresponding check violations. Embodiments normalize the input data tables to include details of circuit nodes, elements, and paths…
Generation of a random sub-space of the space of assignments for a set of generative attributes for verification coverage closure
Granted: February 28, 2017
Patent Number:
9582458
System, method and computer readable medium are described. The method may include obtaining user defined distribution traits characterizing a random sub-space of a space of assignments for a set of generative variables. The method may further include applying the user defined distribution traits on the space of assignments for a set of generative variables to generate the random sub-space of the space of assignments for a set of generative variables. The method may also include testing a…
Using waveform propagation for accurate delay calculation
Granted: February 28, 2017
Patent Number:
9582626
Accurate timing analysis during STA is performed using detailed waveform information in addition to the traditional slew information. A waveform memory system efficiently stores the detailed waveforms that are used in, calculated during, and propagated throughout timing analysis for a circuit design. During the STA process, for multiple modeled stages of circuit design, a waveform including information detailing the form of the waveform is compressed, stored in, decompressed, and…
Method and system for automated refined exclusion of entities from a metric driven verification analysis score
Granted: February 28, 2017
Patent Number:
9582620
A computer implemented method and system for exclusion of entities from a metric driven verification analysis score. The method includes using a processor, and performing the following steps: parsing a source code simulating a device under test and modeling the source code into a model that includes entities of one or a plurality of metric driven entity types; identifying in the source code entities of the same metric driven entity type of said one or a plurality of metric driven entity…
Instruction set to enable efficient implementation of fixed point fast fourier transform (FFT) algorithms
Granted: February 28, 2017
Patent Number:
9582473
A computer implemented method and system for providing a Fast Fourier Transform (FFT) capability to a fixed point processor architecture is disclosed. In a first aspect the computer implemented method and system comprises providing an instruction set within the fixed point architecture. The instruction set includes a plurality of instructions to calculate at least one set of add operations within a FFT butterfly. The plurality of instructions are controlled by a mode register, wherein a…
Method and system for automatically generating executable system-level tests
Granted: February 28, 2017
Patent Number:
9582406
Method and system for automatically generating executable system-level tests. The method includes obtaining a system design including interrelation between components of the system design, actions the components are operable to perform, and constraints relating to the performance of the actions; receiving at least an initial action input to be tested; automatically generating a complete test scenario including: solving a logic layer CSP, including automatically scheduling actions and…
Automated processor generation system and method for designing a configurable processor
Granted: February 28, 2017
Patent Number:
9582278
A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows…
Method, system, and computer program product for checking or verifying shapes in track patterns for electronic circuit designs
Granted: February 7, 2017
Patent Number:
9563737
Methods and systems for checking or verifying shapes in electronic designs are disclosed. The method identifies a dictionary (if pre-existing) or determining the dictionary by creating the dictionary and reduces dimensionality of design data by using a sliced line. Shapes are transformed into sliced line segments along the sliced line. Dictionary entries for shapes are associated with corresponding sliced line segments, and the design is checked or verified using the sliced line segments…
System and method for providing a scalable server-implemented regression query environment for remote testing and analysis of a chip-design model
Granted: January 31, 2017
Patent Number:
9558307
A system and method for providing a scalable server-implemented regression query environment for remote testing and analysis of a chip-design model receives chip-design information, including the chip-design model to be tested and one or more attributes for testing the chip design model; receives a first regression simulation test request from the client-side integration client; initiates a proxy instance for a first regression simulation test to be executed by an application programming…
Methods, systems, and computer-readable media for model order reduction in electromagnetic simulation and modeling
Granted: January 10, 2017
Patent Number:
9542515
Methods, systems, and computer readable media are disclosed for simulating a circuit. The method may comprise a step of providing a network model of the circuit having a plurality of ports, the plurality of ports being associated with one or more net pairs. The method may also comprise combining the plurality of ports into one or more groups based on the net pairs, each group corresponding to a net pair. In addition, the method may comprise calculating, for each group, one or more…
System and method for automatic correction of flight time skew of timing signals in simulated source synchronous interface operation
Granted: January 10, 2017
Patent Number:
9542512
A system and method are provided for maintaining alignment of timing signals of a source synchronous interface between driver and receiver portions of an electronic system in a behavioral model based simulation environment. The system comprises a memory unit, an analysis controller unit coupled to the memory unit, and a timing alignment unit coupled to the analysis controller unit. The timing alignment unit is executable responsive to the analysis controller unit to generate behavioral…
System and method for generating vias in an electronic design by automatically using a hovering cursor indication
Granted: January 10, 2017
Patent Number:
9542084
The present disclosure relates to a computer-implemented method for electronic design automation. The method may include providing, using one or more computing devices, an electronic design. The method may further include receiving an indication that a cursor is hovering over an overlap associated with the electronic design and in response to receiving the indication, computing one or more via parameters, based upon, at least in part, a topology associated with the overlap. The method…
System and method for saddle point locking detection during clock and data recovery
Granted: December 27, 2016
Patent Number:
9531529
The present disclosure relates to a method and apparatus for detecting clock and data recovery loop saddle-point locking in an electronic circuit. Embodiments may include receiving a signal at a primary clock and data recovery (“CDR”) loop associated with the electronic circuit and processing the signal using at least one of a first order CDR loop and a second order CDR loop included within the primary CDR loop. Embodiments may further include determining whether a fast-phase lock…
System and method for generating and using sibling nets model for shared delay calculation across multi-instantiated blocks in the circuit design
Granted: December 27, 2016
Patent Number:
9529962
The present disclosure relates to a computer-implemented method for use with an electronic design. Embodiments include identifying, using one or more processors, a plurality of sibling nets associated with the electronic design and determining if the plurality of sibling nets have a same input slew rate. If the plurality of sibling nets do not have a same input slew rate, embodiments also include determining a delay calculation (DC) for each of the plurality of sibling nets. If the…
Efficient monte carlo flow via failure probability modeling
Granted: December 20, 2016
Patent Number:
9524365
A system, method, and computer program product for automatically reducing the number of Monte Carlo simulation samples required to determine if a design yield is above or below a given yield target with a given confidence. Embodiments perform an initial Monte Carlo based performance modeling using an initial set of statistical samples, and estimate the failure probability of each of the remaining statistical samples based on the performance model. Embodiments then simulate each of the…
