Efficient monte carlo flow via failure probability modeling
Granted: December 20, 2016
Patent Number:
9524365
A system, method, and computer program product for automatically reducing the number of Monte Carlo simulation samples required to determine if a design yield is above or below a given yield target with a given confidence. Embodiments perform an initial Monte Carlo based performance modeling using an initial set of statistical samples, and estimate the failure probability of each of the remaining statistical samples based on the performance model. Embodiments then simulate each of the…
Method and system for creating improved routing polygon abstracts
Granted: December 20, 2016
Patent Number:
9524364
Methods and systems for creating and implementing improved routing polygon abstracts that can be used to efficiently find areas to route through in electrical designs, where the routing polygon abstracts include at least a horizontal routing polygon abstract, a maximum horizontal routing polygon abstract, a vertical routing polygon abstract, and a maximum vertical routing polygon abstract, that are created through various steps including bloating, shrinking, merging, and extending the…
Methods, systems, and articles of manufacture for implementing pattern-based design enabled manufacturing of electronic circuit designs
Granted: December 13, 2016
Patent Number:
9519732
Some embodiments correlate various manufacturing or design information or data with patterns used to represent electronic designs and provide pertinent pattern-based information to metrology, fabrication, or testing tools to enhance their performances of their intended functions. Some embodiments further utilize cross-design or cross-process analytics to perform various pattern-based analyses on electronic designs. Some embodiments perform squish analysis with a squish pattern library on…
Universal single instruction multiple data multiplier and wide accumulator unit
Granted: December 13, 2016
Patent Number:
9519460
A single-instruction multiple-data (SIMD) multiplier-accumulator apparatus and method. A multiplier block with two 16-bit by 32-bit multiplier circuits transform a selectable number of input multipliers and multiplicands into a selected number of products. Each multiplier circuit comprises an array of full adders that generates and sums partial products using carry-save addition. An accumulator block, with additional data width to help prevent overflow, adds the products to a selectable…
Optimized fused-multiply-add method and system
Granted: December 13, 2016
Patent Number:
9519458
A fused-multiply-add system is disclosed. The fused-multiply-add system includes a multiplier to multiply first and second operands and to provide at least one product. The fused-multiply-add system also includes an alignment shifter for aligning a third operand with the at least one product to provide an aligned third operand. The fused-multiply-add system also includes an adder and a subtractor coupled to the multiplier and the alignment shifter for performing two asymmetrical…
Coverage driven generation of constrained random stimuli
Granted: December 6, 2016
Patent Number:
9514035
A method, system and computer readable medium for coverage driven generation of stimuli for DUT verification. The method may include receiving, via an input device, a generation model and a coverage model from a user. The method may also include using a processor, identifying a coverage item in the coverage model and finding a corresponding element in the generation model corresponding to the coverage item. The method may further include using a processor translating a coverage…
Method for using XOR trees for physically efficient scan compression and decompression logic
Granted: December 6, 2016
Patent Number:
9513335
Methods and apparatus for decompressing test data using XOR trees for application to scan chains of a design for test (DFT) integrated circuit in a physically efficient construction are disclosed. Moreover, methods and apparatus for compressing test response data from scan chains in a DFT integrated circuit in a physically efficient construction are disclosed. The XOR tree decompression method may comprise splitting signals at each node of the XOR trees according to distribution logic…
Automatic harmonic number identification for harmonic balance analysis
Granted: November 29, 2016
Patent Number:
9507894
An apparatus and method for identifying an optimal harmonic number of a circuit are disclosed. In a simulation of the circuit, a periodic input waveform up to a particular number of periods is applied to the modeled circuit and an output waveform is obtained in response. In response to detection of a steady state response of the output waveform, embodiments simulate the circuit by applying an additional period of the periodic input waveform and obtaining the output waveform corresponding…
Methods, systems, and articles of manufacture for implementing analog behavioral modeling and IP integration using systemverilog hardware description language
Granted: November 22, 2016
Patent Number:
9501592
Some embodiments provide support for real number modeling in SystemVerilog by defining built-in nettypes with real data type and resolution functions natively in SystemVerilog and allow a simple path for porting Verilog-AMS wreal modeling to SystemVerilog modeling. Some embodiments provide support for incompatible nettypes and for net coercion in SystemVerilog. Some embodiments provide support for SystemVerilog reals net connecting to electrical nets and support for SystemVerilog real…
System and method for assertion publication and re-use
Granted: November 22, 2016
Patent Number:
9501598
A system and method for managing analog assertion publication and re-use for analog and mixed-signal circuit designs. A graphical user interface based environment allows circuit designers to create, verify, formalize, and publish an analog assertion for a circuit design for subsequent re-use with another circuit design. Embodiments enable analog assertion handling while simultaneously depicting a circuit design in a schematic and/or layout editor window. Embodiments capture referenced…
Systems and methods for testing integrated circuit designs
Granted: November 22, 2016
Patent Number:
9501590
A CoDec in a design for test integrated circuit. In embodiments described herein, portions of the CoDec are distributed over the area of the IC. In particular, both the compressor and the decompressor may be distributed over the IC. To this end, XOR gates are located locally to the scan chains over the area of the chip to reduce wire length back to the input/output test pins. The compressor and decompressor may be distributed in a 2-dimensional grid. The compressor may XOR each scan…
Implementing synchronous triggers for waveform capture in an FPGA prototyping system
Granted: November 15, 2016
Patent Number:
9495492
An apparatus and method for implementing synchronous triggers for waveform capture in a multiple FPGA system is described. The apparatus includes trigger net circuitry that has one or more trigger nets and an output. Furthermore, a plurality of programmable logic devices are provided with each logic device including logic circuitry that is programmable to correspond to a circuit design, a logic analyzer circuit that includes logic connections coupled to the logic circuitry to monitor…
System and method for selectively coupled parasitic compensation for input referred voltage offset in electronic circuit
Granted: November 8, 2016
Patent Number:
9490795
A system and method are provided for selectively coupled parasitic compensation for voltage offset in an electronic circuit. At least one compensation cell is coupled to an input stage for the circuit. The compensation cell includes an isolation node disposed in spaced manner from control and sampling nodes defined by the input stage. The isolation node is configured to form first and second parasitic capacitances respectively with the control and sampling nodes during system operation.…
Microphone interface and IP core for always-on system
Granted: October 25, 2016
Patent Number:
9478231
Methods and systems provide a partitioned IP core and hierarchical power management to reduce power consumption and footprint size of an “always-on” pulse density modulation (PDM) sensor system. The IP core may be partitioned into a register transfer level (RTL) block and a firmware block. The RTL may include a first stage decimation filter, storage, and, optionally, a sound energy detector. The firmware block may include subsequent decimation filter(s) and sensor processing logic,…
Isolating differences between revisions of a circuit design
Granted: October 25, 2016
Patent Number:
9477802
An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and…
System, method, and computer program product for automatically selecting a constraint solver algorithm in a design verification environment
Granted: October 25, 2016
Patent Number:
9477800
The present disclosure relates to a computer-implemented method for electronic design verification. Embodiments may include providing, using one or more processors, an electronic design verification environment having a plurality of randomize calls associated therewith. Embodiments can also include selecting one of the plurality of randomize calls for analysis at a constraint solver engine and iteratively analyzing the selected randomize call using a plurality of constraint solver…
Bit-level register file updates in extensible processor architecture
Granted: October 25, 2016
Patent Number:
9477473
This document discusses, among other things, systems and methods to receive an instruction to selectively update a value of one or more selected bits of a first register, to receive the one or more selected bits of the first register to be updated and one or more selected bits of the first register to remain unchanged, and to selectively update the value of the one or more selected bits of the first register using a first write port without receiving the value of the one or more selected…
Elastic compression-optimizing tester bandwidth with compressed test stimuli using overscan and variable serialization
Granted: October 18, 2016
Patent Number:
9470754
Systems and methods disclosed herein provide for utilizing extra variables in the decompression equation set of an ATPG process for test patterns requiring an excess number of care bits than can be supported efficiently by the current hardware. An elastic interface is utilized between a tester and a decompressor network (e.g., sequential and combinational decompressors) in order to expand the test pattern length and/or the number of input variables. The systems and methods also provide…
Method for using sequential decompression logic for VLSI test in a physically efficient construction
Granted: October 18, 2016
Patent Number:
9470756
Methods, systems, and integrated circuits for decompressing a set of scan input data in a Design for Test (DFT) application, in which implementation may include determining a number of scan inputs to applied circuit from automated test equipment (ATE). Based on the number of scan inputs, another aspect of implementation may involve generating a 2-dimensional grid on the integrated circuit (IC). Another implementation aspect may involve decompressing the scan inputs from the ATE according…
Method for dividing testable logic into a two-dimensional grid for physically efficient scan
Granted: October 18, 2016
Patent Number:
9470755
Methods and computer-readable media for effecting physically efficient scans of integrated circuit designs may include selecting a two-dimensional grid size for exposure to the method, the two-dimensional grid having a size that includes a first side length, a second side length, and a number of flops. The method is performed to select a two-dimensional grid size that maximizes compression efficiency and limit wiring congestion on the IC. In one aspect, the method may be performed on…
