Adaptive deadend avoidance in constrained simulation
Granted: March 11, 2014
Patent Number:
8671395
The present disclosure relates to a method for avoiding deadends in a constrained simulation. The method may include analyzing a first deadend during a simulation and a first constraint of the simulation. The method may further include determining if the first constraint causes the first deadend. If the first constraint causes the first deadend, the method may also include defining a first lookahead constraint corresponding to the first constraint. The method may additionally include…
System, method, and computer program product for optimizing pins
Granted: March 4, 2014
Patent Number:
8667454
The present disclosure relates to a computer-implemented method for synthesis of device I/O associated with a printed circuit board (PCB) design. The method may include generating a first programmable device model and a second device model. The method may further include determining one or more pin assignments associated with the first programmable device model and the second device model based upon, at least in part, one or more of a breakout pattern, a breakout location and a fanout…
Circuit simulation methodology to calculate leakage current during any mode of circuit operation
Granted: March 4, 2014
Patent Number:
8667442
A method for calculating leakage current associated with an integrated circuit, includes selecting a sampling point at which an input signal for the integrated circuit is in a quiescent state and determining the leakage current associated with the integrated circuit using the selected sampling point.
Phase noise analysis of oscillator circuit designs
Granted: March 4, 2014
Patent Number:
8666689
In one embodiment of the invention, a method and a system for phase noise analysis of oscillators is provided using frequency aware perturbation projection vector techniques. The method and system includes performing steady state analysis on the oscillator by generating an augmented Jacobian matrix. A transfer function for frequency deviation is extracted for the augmented Jacobian matrix for a predetermined frequency range including the oscillation frequency of the oscillator. The phase…
Method and apparatus for AMS simulation of integrated circuit design
Granted: February 25, 2014
Patent Number:
8661402
A method to create an integrated circuit that includes digital and analog components comprising: displaying on a computer system display, user input to the computer system that specifies parameter information to determine a binding between an analog circuit design component and a digital circuit design component; saving the user specified parameter information within a file that also specifies at least a portion of the analog circuit design; associating the analog circuit design…
Frequency division multiplexing (FDM) lithography
Granted: February 25, 2014
Patent Number:
8661375
Systems and methods for generating an image are provided. These systems and methods include generating multiple light beams from a light source by controlling at least one parameter of the light source to be different among each of the multiple light beams. The systems and methods further include forming multiple light patterns of circuit structures that are separated in frequency by directing each of the light beams at a mask of circuit features. The systems and methods, when used in…
Method and apparatus for fixing double patterning color-seeding violations
Granted: February 25, 2014
Patent Number:
8661371
A method for displaying layout-fixing hints for resolving color-seeding violations in an IC design layout. The method receives a set of error paths within a disjoint set of shapes. For each error path, the method performs an analysis on the error path to identify a set of layout-fixing hints that eliminates the color-seeding violation on the error path and does not introduce any new color-seeding violation. The method displays the set of identified hints for each error path in order to…
System and method for implementing power integrity topology adapted for parametrically integrated environment
Granted: February 18, 2014
Patent Number:
8656329
A system and method are provided for generating a programmably implemented model which emulates a power delivery network serving an integrated circuit (IC) core in an electronic system. The system and method generally comprise measures for establishing a power integrity (PI) topology including models for a voltage regulator module that generates at least one predetermined supply voltage level, and for a conductive power rail portion of the power delivery network (PDN). The system and…
System, method, and computer program product for abstract software performance profiling
Granted: February 18, 2014
Patent Number:
8656368
The present disclosure relates to a computer-implemented method for abstract software performance profiling. The method may include providing, using a computing device, a virtual run-time stack associated with a software performance profile. The method may further include generating, using the computing device, at least one abstract tag associated with the virtual run-time stack. The method may also include performing, using the computing device, at least one operation on the virtual…
Apparatus with general numeric backtracking algorithm for solving satisfiability problems to verify functionality of circuits and software
Granted: February 18, 2014
Patent Number:
8656330
In one embodiment of the invention, a design verifier is disclosed including a model extractor and a bounded model checker having an arithmetic satisfiability solver. The arithmetic satisfiability solver searches for a solution in the form of a numeric assignment of numbers to variables that satisfies each and every one of the one or more numeric formulas. Conflict in the search, results in the deduction of one or more new numeric formulas that serve to guide the search toward a…
Circuit design systems for replacing flip-flops with pulsed latches
Granted: February 18, 2014
Patent Number:
8656324
A circuit design system, methodology, and software are disclosed for generating circuit capable of consuming less dynamic power. In particular, the circuit design methodology entails modifying an initial circuit design including a clock network coupled to a plurality of edge-triggered flip-flops to generate a modified circuit design that uses pulsed latches driven by pulse generators in place of at least some of the flip-flops. Since pulsed latches use less dynamic power than…
Method of eliminating a lithography operation
Granted: February 18, 2014
Patent Number:
8656321
Methods of semiconductor device fabrication techniques using double patterning are disclosed. According to various embodiments of the invention, methods of semiconductor device fabrication using self-aligned double patterning are provided. Particular embodiments of the invention allow creation of logic circuit patterns using two lithographic operations. One embodiment of the invention employs self-aligned double patterning to define two or more sets of parallel line features with a…
Method and apparatus for low-pin count testing of integrated circuits
Granted: February 11, 2014
Patent Number:
8650524
A method and apparatus to apply compressed test patterns using a very pin-limited test apparatus to a chip design for use in semiconductor manufacturing test is disclosed. Compression circuitry is inserted into the circuit design and the compressed signals manipulated for communication over a serial interface. On a test apparatus, ATPG may be run, assuming a parallel test interface, resulting in test patterns that may be compressed into a parallel format and then converted into a serial…
Method and apparatus for rule-based automatic layout parasitic extraction in a multi-technology environment
Granted: February 11, 2014
Patent Number:
8650518
A system for extracting a layout from an object in a fabric includes means for providing fabric data to a rule-based layout extraction engine; means for maintaining a layout extraction rule to select a layout object from the fabric data; means for maintaining a binding rule to bind the layout object to a solver; means for maintaining a boundary rule to specify a boundary condition for a solver; and means for executing the solver on the layout object to generate a model of the object.
Methods, systems, and computer program products for implementing interactive coloring of physical design components in a physical electronic design with multiple-patterning techniques awareness
Granted: February 4, 2014
Patent Number:
8645902
Various embodiments provide a constraint-driven environment to interactively determine coloring of layout components when the layout components are being modified or created and to provide feedback with visual aids to users in nearly real-time. Layout components are thus appropriately assigned to respective mask designs upon their creation. Various embodiments check or verify various constraints during creation or modification of layout components, and the layout thus remains design rule…
Visualization and information display for shapes in displayed graphical images based on a cursor
Granted: February 4, 2014
Patent Number:
8645901
Graphical viewing of shapes and descriptive information in displayed graphical images. In one aspect, shape information is displayed in a graphical interface using a computer system and includes causing a display of an image and one or more shapes in the image, and causing a display of a cursor. Labels are also displayed, each of the labels associated with a different one of the displayed shapes. The plurality of labels are displayed within a predetermined zone relative to a displayed…
Configuration and analysis of design variants of multi-domain circuits
Granted: February 4, 2014
Patent Number:
8645894
A circuit design system generates a circuit variant by relocating one or more circuit elements through a user move action on a user interface. When the user move action results in the circuit element traversing a circuit domain boundary, the design system performs one or more operations to form the circuit variant having its initial connectivity with the relocated circuit element without any other user action on the user interface than the user move action. Further, in response to no…
Method and system for model-based design and layout of an integrated circuit
Granted: February 4, 2014
Patent Number:
8645887
A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.
Methods and apparatus for performing statistical static timing analysis
Granted: February 4, 2014
Patent Number:
8645881
A method and an apparatus to perform statistical static timing analysis have been disclosed. In one embodiment, the method includes performing statistical analysis on performance data of a circuit from a plurality of libraries at two or more process corners using a static timing analysis module, and estimating performance of the circuit at a predetermined confidence level based on results of the statistical analysis during an automated design flow of the circuit without using libraries…
Method for multiple processor system-on-a-chip hardware and software cogeneration
Granted: January 28, 2014
Patent Number:
8639487
An automated system-on-chip (SOC) hardware and software cogeneration design flow allows an SOC designer, using a single source description for any platform-independent combination of reused or new IP blocks, to produce a configured hardware description language (HDL) description of the circuitry necessary to implement the SOC, while at the same time producing the development tools (e.g., compilers, assemblers, debuggers, simulator, software support libraries, reset sequences, etc.) used…
