System and method for abutment in the presence of dummy shapes
Granted: April 8, 2014
Patent Number:
8694941
A system and method for optimizing a design layout by identifying features for abutment where the shapes that trigger the abutment are overlapping, within a predefined proximity of each other, or are interface elements for features having a short circuit. The abutment process may identify shapes for abutment that are not connected to a netlist of the design or are otherwise not associated with a connection pin. The abutment process may adjust a shape or feature including, for example by…
Method and apparatus for multi-die thermal analysis
Granted: April 8, 2014
Patent Number:
8694934
Some embodiments of the invention provide a method for performing thermal analysis of a multi-die integrated circuit (IC) design layout. The thermal analysis produces a temperature distribution for analyzing internal properties of each die within the multi-die design and for analyzing thermal interactions between two or more dies of the design based on an internal configuration of the two or more dies. Therefore, in some embodiments, the temperature distribution shows a temperature…
Methods, systems, and articles of manufacture for implementing electronic circuit designs with simulation awareness
Granted: April 8, 2014
Patent Number:
8694933
Disclosed are methods, systems, and articles of manufacture for implementing electronic designs with simulation awareness. A schematic is identified or created and simulated at the schematic level to characterize the functional behavior of the circuit or to ensure the circuit design meets the required design specifications. Physical data of a component of the design is identified, created, or updated, and the electrical parasitic associated with physical data is characterized. One or…
Systems and methods for super-threading of integrated circuit design programs
Granted: April 8, 2014
Patent Number:
8694931
In one embodiment of the invention, a method is disclosed including receiving a netlist of an integrated circuit design; executing a first copy of an integrated circuit design program with a first processor associated with a first memory space to independently perform work on a first portion of the integrated circuit design; and executing a second copy of the integrated circuit design program with a second processor associated with a second memory space to independently perform work on a…
Method and apparatus for detecting trapping sets in decoding of information
Granted: April 1, 2014
Patent Number:
8689074
Decoding information using error-correcting codes includes, in one aspect, receiving transmitted information that includes original information coded using an error correction coding technique, and using at least one processor to iteratively decode the transmitted information to correct transmission errors and determine the original information. The iterative decoding includes determining that the iterative decoding has become trapped in a trapping set before a predetermined maximum…
Predictive run testing
Granted: April 1, 2014
Patent Number:
8689187
A test object can be selectively included in a test run based on predicting the behavior of the test object. In one embodiment, the present invention includes predicting how likely the test object is to produce a failure in a test run and deciding whether to include the test object in the test run based on the predicted likelihood. This likelihood of producing a failure may be based on any number of circumstances. For example, these circumstances may include the history of prior failures…
Method, apparatus, and article of manufacture for providing in situ, customizable information in designing electronic circuits with electrical awareness
Granted: April 1, 2014
Patent Number:
8689169
Disclosed are a method, system, and computer program product for providing customizable information in designing electronic circuits with electrical awareness. The method or the system displays a portion of a physical design of an electronic circuit in a first display area. The method or the system receives or identifies a user's or a system's manipulation of the portion of the physical design of the electronic circuit. The method or the system then determines and displays an in situ…
Extracting capacitance and resistance from FinFET devices
Granted: April 1, 2014
Patent Number:
8689157
Some embodiments of the invention provide a method for verifying an integrated circuit (IC) design. The method receives a process description file that specifies a process technology for building the IC. The process description file describes a particular device type in which a first conductor overlaps a second conductor by recessing from the second conductor in one or more cut-outs. Based on the process description file, the method finds a section of the IC design that matches the…
System and method for management of controls in a graphical user interface
Granted: April 1, 2014
Patent Number:
8689121
Management of controls in a graphical user interface (GUI) of a computer system. In one aspect, a command is received to create and display a window in the GUI, the window including one or more controls, each control operative to perform a function of an application in response to selection. An associated scope for each control is determined and indicates an extent of shared use of the control within the GUI. It is determined if a different instance of the control already exists within…
Method and apparatus for breaking trapping sets in decoding of information
Granted: April 1, 2014
Patent Number:
8689084
Decoding information using error-correcting codes includes, in one aspect, receiving transmitted information that includes original information coded using an error correction coding technique, and using at least one processor to iteratively decode the transmitted information to correct transmission errors and determine the original information. The iterative decoding includes, in response to becoming trapped in a trapping set, adjusting information used in the iterative decoding and…
Power domain crossing interface analysis
Granted: March 25, 2014
Patent Number:
8683419
A method is provided to test an integrated circuit design for power management circuit design errors comprising: configuring a computer to identify multiple power domain crossing paths between pairs of power domains; identify one or more power related constraints associated with such power domain crossing paths; and group power domain crossing paths between matching power domain pairs that are associated with matching power related constraints.
Method and system for optimizing placement of I/O element nodes of an I/O ring for an electronic design
Granted: March 25, 2014
Patent Number:
8683412
Disclosed are improved methods, systems, and computer program products for generating and optimizing an I/O ring arrangement for an electronic design. Corner packing is one approach that can be taken to optimizing an I/O ring. Stacking of I/O components provides another approach for optimizing an I/O ring.
System and method for fault sensitivity analysis of mixed-signal integrated circuit designs
Granted: March 25, 2014
Patent Number:
8683400
A apparatus and method for conducting fault sensitivity analysis of the analog portions of a mixed signal circuit design includes simulating the fault free circuit design, inserting a fault into the analog portion of the circuit design, simulating the circuit design with the fault during a fault interval time period, and determining whether the fault is detectable.
Method for self-aligned doubled patterning lithography
Granted: March 25, 2014
Patent Number:
8679981
Various embodiments of the invention provide systems and methods for semiconductor device fabrication and generation of photomasks for patterning a target layout of line features and large features. Embodiments of the invention are directed towards systems and methods using self-aligned double pattern to define the target layout of line features and large features.
Method and system for implementing die size adjustment and visualization
Granted: March 18, 2014
Patent Number:
8677307
Disclosed are improved methods, systems, and computer program products for visualizing and estimating IC die arrangement for an electronic design, and for performing chip planning and estimation based upon the estimated and visualized IC die arrangements. According to some approaches, an interface is provided for visualizing different die arrangement options for an electronic design, in which a filmstrip view is provided to display smaller images of different die arrangement options, and…
Method and system for model-based design and layout of an integrated circuit
Granted: March 18, 2014
Patent Number:
8677301
A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.
Abstraction-aware distributed window configurations in complex graphical user interfaces
Granted: March 18, 2014
Patent Number:
8677260
A user interface to an application processing complex data of multiple data view abstractions allows selection, placement, size and other configurable characteristics of interface components to be controlled by a user and then associated with the data abstraction and processing task. Multiple configurations may be created to simplify the interface to include only necessary controls given an abstraction level of the data view and the task on that data. The configurations may be stored…
Low cost production testing for memory
Granted: March 18, 2014
Patent Number:
8677196
Embodiments provide methods, systems, devices, and/or machine readable storage medium for memory built-in self testing (memory BIST) that may not require JTAG. Embodiments may provide less chip overhead through the use of one or more direct access pins. Embodiments may provide simple checks to determine if the memories on a chip are good or bad with minimal cost, for example. In some cases, the memory BIST may determine whether or not memories are good when the chip powers on. Some…
Method, system, and program product to implement detail routing for double pattern lithography
Granted: March 11, 2014
Patent Number:
8671368
Disclosed are a method, apparatus, and computer program product to implement routing for double patterning lithography. A three-phase routing scheme is employed, comprising a global router, a C-router, and a detail router. The C-router provides double patterning color seeding for routing tracks in the electronic design. The detail router employs space-tiles to perform double-patterning based routing for wires in the electronic design.
Method and system for distributing clock signals on non manhattan semiconductor integrated circuits
Granted: March 11, 2014
Patent Number:
8671378
The present invention introduces methods, systems, and architectures for routing clock signals in an integrated circuit layout. The introduced clock signal clock signal structures are rendered with non Manhattan routing. In a first embodiment, the traditional recursive H clock signal structure is rendered after transforming the coordinates system such that a rotated recursive H clock signal structure is rendered. In another embodiment, a recursive Y structure is used to create a clock…
