Method for connecting flip chip components
Granted: December 3, 2013
Patent Number:
8601429
An automated system and method for determining flip chip connections involves generating a first projection that includes representations of bumps arranged over a core of the flip chip and generating a second projection that includes representations of I/O pads arranged around the core. The first projection is generated by drawing a line through each bump between a location of the flip chip and an outer portion of the flip chip and marking a location where the line terminates at the…
Method and system for schematic-visualization driven topologically-equivalent layout design in RFSiP
Granted: December 3, 2013
Patent Number:
8601422
An improved approach for automatically generating physical layout constraints and topology that are visually in-sync with the logic schematic created for simulation is described. The present approach is also directed to an automatic method for transferring topology from logic design to layout.
Equivalent waveform model for static timing analysis of integrated circuit designs
Granted: December 3, 2013
Patent Number:
8601420
In one embodiment, a method of constructing an equivalent waveform model for static timing analysis of integrated circuit designs is disclosed. The method includes fitting time point coefficients (qk) and known time delay values from a delay and slew model of a receiving gate from a timing library; determining waveform values (Ikj) for input waveforms from the timing library; determining timing values (dj) from a timing table in the timing library in response to the input waveforms of…
Netlisting analog/mixed-signal schematics to VAMS
Granted: December 3, 2013
Patent Number:
8601412
A method is provided to convert an analog mixed-signal schematic design to a digital netlist: digital blocks within the schematic design are converted to digital netlist modules; analog blocks within the schematic design are converted to analog netlist modules: at least one digital netlist module includes a first identifier for a component that is shared between at least one digital block and at least one analog block within the schematic design; an analog netlist module that corresponds…
System and method for providing compact mapping between dissimilar memory systems
Granted: November 26, 2013
Patent Number:
8594991
A memory mapping system for compactly mapping dissimilar memory systems and methods for manufacturing and using same. The mapping system maps a source memory system into a destination memory system by partitioning the source memory system and disposing memory contents within the partitioned source memory system into the destination memory system. In one embodiment, the mapping system factorizes a source data width of the source memory system in terms of a destination data width of the…
Generating user clocks for a prototyping environment
Granted: November 26, 2013
Patent Number:
8595683
A method and apparatus for generating user clocks in a prototyping system is disclosed. A prototyping system has a plurality of programmable logic chips that are each programmed with one or more partition of a prototyped circuit design. For a circuit design having multiple user clock signals, each partition uses some or all of the user clocks. A reference clock signal is externally generated, and received by each of the programmable logic chips. Using a phase-locked loop, a plurality of…
Method and apparatus to use physical design information to detect IR drop prone test patterns
Granted: November 26, 2013
Patent Number:
8595681
A method is provided to evaluate whether one or more test patterns is power safe for use during manufacturing testing of an integrated circuit that includes a nonuniform power grid and that includes a scan chain, the method comprising: assigning respective toggle count thresholds for respective power grid regions of the non-uniform power grid; and determining whether respective numbers of toggles by scan elements of the scan chain within one or more respective power grid regions meet…
Method and system for performing voltage-based fast electrical analysis and simulation of an electronic design
Granted: November 26, 2013
Patent Number:
8595677
A system, method, and computer program product is disclosed for performing electrical analysis of a circuit design. A voltage-based approach is described for performing two-stage transient EM-IR drop analysis of an electronic design. A two-stage approach is performed in some embodiments, in which the first stage operates by calculating the voltage at certain interface nodes. In the second stage, simulation is performed to simulate the circuit to concurrently obtain the current at the…
Flexible noise and delay modeling of circuit stages for static timing analysis of integrated circuit designs
Granted: November 26, 2013
Patent Number:
8595669
Systems, apparatus, and methods of static timing analysis for an integrated circuit design in the presence of noise are disclosed. The integrated circuit design may be partitioned into a plurality of circuit stages. A timing graph including timing arcs is constructed to represent the timing delays in circuit stages of the integrated circuit design. A model of each circuit stage may be formed including a model of a victim driver, an aggressor driver, a victim receiver, and a victim net…
Methods, systems, and articles of manufacture for implementing a physical design of an electronic circuit with automatic snapping
Granted: November 26, 2013
Patent Number:
8595662
Disclosed are methods and systems for providing a constraint-driven environment for implementing a physical design of an electronic circuit with automatic snapping. In some embodiments, the method identifies or creates an incomplete layout. The method identifies an object and constraints for the object. The method then identifies an approximate position for the object in the layout and automatically snaps the object to a drop location based on the approximate position while complying…
Method and apparatus for circuit simulation using parallel computing
Granted: November 26, 2013
Patent Number:
8594988
In one embodiment of the invention, a method of analyzing a circuit design is disclosed. In the method of analyzing a circuit design, a circuit is levelized into multiple levels. Circuit simulations of elements at a level are determined using circuit simulators, one for each element and in parallel in level order. Topological circuit loops may be removed from the circuit. Circuit simulation of the circuit may be performed on the circuit using the circuit simulations determined by the…
Statistical corner extraction using worst-case distance
Granted: November 19, 2013
Patent Number:
8589852
Certain circuit models include design parameters that reflect user choices and statistical parameters that reflect modeling uncertainty. For each performance goal (e.g., a one-sided performance goal), a closest point of failure in the statistical parameters is used to identify a statistical corner that characterizes a specified tolerance for that performance goal. Adjusting the design parameters to improve performance for these corners improves overall performance and corresponding…
Testing to prescribe state capture by, and state retrieval from scan registers
Granted: November 12, 2013
Patent Number:
8584074
State retention cells of a test circuit embedded in an electrical circuit are interconnected to form one or more scan chains. The scan chains are interconnected so that unknown states, or X-states, are shifted through the scan chains in an order other than the order in which the states were captured by the state retention cells of the scan chain. Such reordering of response states in individual scan chains may be used to align the X-states across multiple scan chains to achieve higher…
Technique for modeling parasitics from layout during circuit design and for parasitic aware circuit design using modes of varying accuracy
Granted: November 12, 2013
Patent Number:
8584072
A user is presented with a simulation environment within which the user is provided a choice to select between parasitic simulation modes of varying accuracy, the modes including a mode without parasitics and a plurality of modes including parasitics with a varying degree of accuracy. A selection from among the modes is received from the user and simulation test are performed at the selected degree of accuracy.
Method and apparatus for AMS simulation of integrated circuit design
Granted: November 5, 2013
Patent Number:
8578322
A method to create an integrated circuit that includes digital and analog components comprising: displaying on a computer system display, user input to the computer system that specifies parameter information to determine a binding between an analog circuit design component and a digital circuit design component; saving the user specified parameter information within a file that also specifies at least a portion of the analog circuit design; associating the analog circuit design…
System and method for simulating a bi-directional connect module within an analog and mixed-signal circuit
Granted: October 29, 2013
Patent Number:
8571837
According to some embodiments, a method is provided for simulating an analog and mixed-signal circuit design comprising an analog circuit segment connected to a digital circuit segment at a connection point, the method comprising: inserting a bi-directional interface element at the connection point, wherein the analog circuit segment connects to an analog port of the bi-directional interface element and the digital circuit segment connects to a digital port of the bi-directional…
Method and system for approximate placement in electronic designs
Granted: October 29, 2013
Patent Number:
8572540
Disclosed are method, system, and computer program product for a method and system for a fast and stable placement/floorplanning method that gives consistent and good quality results. Various embodiments of the present invention provide a method and system for approximate placement of various standard cells, macro-blocks, and I/O pads for the design of integrated circuits by approximating the final shapes of the objects of interest by one or more probability distribution functions over…
Common path pessimism removal for hierarchical timing analysis
Granted: October 29, 2013
Patent Number:
8572532
A method of timing analysis of an integrated circuit (IC) design with a partition block including an original clock signal with a pair of clock paths having an external common point outside the block boundary is disclosed, including receiving a netlist of the partition block of a hierarchical IC design, analyzing a pair of clock paths having the external common point to determine first and second clock ports at the boundary of the partition block; and for the first and second clock…
System and method for dynamically injecting errors to a user design
Granted: October 29, 2013
Patent Number:
8572529
A method and system for dynamically injecting errors to a user design is disclosed. In one embodiment, the user design having internal states and parameters is run in a design verification system. A reconfigurable design monitor monitors a plurality of error conditions based on the internal states and parameters of the user design and generates a trigger event when a predefined error condition is met. The reconfigurable design monitor transmits a trigger event to an error injector. The…
System and method for modifying a data set of a photomask
Granted: October 29, 2013
Patent Number:
8572517
The present invention provides a method for compensating infidelities of a process that transfers a pattern to a layer of an integrated circuit, by minimizing, with respect to a photomask pattern, a cost function that quantifies the deviation between designed and simulated values of circuit parameters of the pattern formed on a semiconductor wafer.
