Methods and mechanisms for extracting and reducing capacitor elements
Granted: October 29, 2013
Patent Number:
8572545
A method of extracting capacitance from a layout record includes imposing voltages on conductors in a layout record, and determining a total charge for each of the conductors to obtain a capacitor element for the conductors. A method of extracting capacitance from a layout record includes matching a configuration of conductors in a layout record against a reference pattern, and determining an extracted capacitance for the conductors based at least in part on the reference pattern. A…
System and method for parametric intercoupling of static and dynamic analyses for synergistic integration in electronic design automation
Granted: October 22, 2013
Patent Number:
8566767
A system and method are provided for actuating static and dynamic analysis tools in parametrically intercoupled manner for synergistic optimization of an electronic system design. The system and method execute a timing designer process for selectively actuating the static analysis tool to conduct timing analysis based on at least one predetermined timing model and generate a plurality of estimated values for certain signal parameters to be in compliance with predetermined timing…
Method and apparatus for multi-die thermal analysis
Granted: October 22, 2013
Patent Number:
8566760
Some embodiments of the invention provide a method for performing thermal analysis of a multi-die integrated circuit (IC) design layout. The thermal analysis produces a temperature distribution for analyzing internal properties of each die within the multi-die design and for analyzing thermal interactions between two or more dies of the design based on an internal configuration of the two or more dies. Therefore, in some embodiments, the temperature distribution shows a temperature…
Method, system, and program product to implement C-routing for double pattern lithography
Granted: October 15, 2013
Patent Number:
8560998
Disclosed are a method, apparatus, and computer program product to implement routing for double patterning lithography. A three-phase routing scheme is employed, comprising a global router, a C-router, and a detail router. The C-router provides double patterning color seeding for shapes on routing tracks in the electronic design. The detail router employs space-tiles to perform double-patterning based routing for wires in the electronic design.
Automatic debugging using automatic input data mutation
Granted: October 15, 2013
Patent Number:
8560991
Embodiments provide systems, devices, methods, and machine-readable medium for automated debugging of a design under test in a verification environment as part of electronic design automation. Embodiments may automatically identify inputs that are relevant to a bug for a device under test. A failing test run may be taken and rerun several times with small changes in the inputs. If the test is passing, the mutated inputs may be important to reproduce the bug and may be marked as…
Configuration-based merging of coverage data results for functional verification of integrated circuits
Granted: October 15, 2013
Patent Number:
8560985
In one embodiment of the invention, a method for verification of an integrated circuit design is disclosed. The method includes independently executing simulation runs in response to a plurality of coverage models to respectively generate a plurality of coverage data for a plurality of functional blocks within one or more integrated circuit designs; generating a target coverage model to selectively merge at least first coverage data associated with a first coverage model and second…
Methods and systsm for physical layout estimation
Granted: October 15, 2013
Patent Number:
8560984
In one embodiment of the invention, a physical layout wire-load algorithm is used to generate a wire-load model based on physical data including aspect ratio and wire definitions defined in a physical library. The physical layout estimator is utilized to dynamically produce the physical layout wire-load model and to calculate net length and delay for each optimization iteration.
Systems and methods for automatically generating executable system level-tests from a partially specified scenario
Granted: October 15, 2013
Patent Number:
8560893
A method and system are provided for automatically generating executable system-level tests from an initial action or partially specified scenario by accumulating necessary complement actions and forming a set of constraints required by the initial action and the necessary complement actions. The set of constraints is solved by a constraint solving engine to provide an at least partial sequence of the actions and parameters thereto that satisfies the set of constraints. The sequence of…
Method and system for bi-directional communication between an integrated circuit (IC) layout editor and various IC pattern data viewers
Granted: October 15, 2013
Patent Number:
8560109
Various embodiments of the present invention relate to bi-directional communication between an Integrated Circuit (IC) layout editor and various generic layout and/or pattern data viewers. Further, the present invention provides a bi-directional control between the IC layout editor and the various generic layout and/or pattern data viewers and allows substantially simultaneous display of an IC design in various IC mask layout data formats. The IC layout editor and the various generic…
Method and apparatus for design rule violation reporting and visualization
Granted: October 8, 2013
Patent Number:
8555237
An apparatus and method for reporting design rule violations of an integrated circuit design includes collecting data from a design rule checker module, processing the data, and displaying design rule violations onto the layout. The display of the design rule violations may be interactive by including hypertext links to specifications, text bubbles with violation explanations, measurements, highlighting areas of the layout corresponding to a particular rule, and providing hierarchically…
Methods, systems, and articles of manufacture for implementing a physical design of an electronic circuit with automatic snapping
Granted: October 8, 2013
Patent Number:
8555223
Disclosed are methods and systems for providing a constraint-driven environment for implementing a physical design of an electronic circuit with automatic snapping. In some embodiments, the method identifies or creates an incomplete layout. The method identifies an object and constraints for the object. The method then identifies an approximate position for the object in the layout and automatically snaps the object to a drop location based on the approximate position while complying…
Methods and systems for property assertion in circuit simulation
Granted: October 8, 2013
Patent Number:
8554530
Systems and methods for simulating and verifying a design are contemplated. Various embodiments determine a set of verification rules for a design, wherein the verification rules use a PSL or SVA syntax in a SPICE netlist to describ a property of the circuit design. The state of a circuit at a simulated first time, t1, can be determined. The state at the first time, t1, may be analyzed to determine if a triggering event has occurred. Based on the occurrence of the triggering event, the…
Method and apparatus to provide machine-assisted training
Granted: October 8, 2013
Patent Number:
8554130
A method and an apparatus to provide machine-assisted training have been disclosed. In one embodiment, the method includes monitoring action performed by a trainee during machine-assisted training and dynamically adjusting the machine-assisted training in response to the trainee's action. Other embodiments have been claimed and described.
Systems for automatic circuit routing with object oriented constraints
Granted: October 1, 2013
Patent Number:
8549459
In one embodiment of the invention, an object oriented autorouter is disclosed for routing nets in a circuit. The object oriented autorouter includes a routing data model (RDM); at least one routing engine, such as a single connection router (SCR), a topographical (TOPO) transformation engine, and a detail geometric (DETAIL) engine, and a command and control module (CCM) coupled together. The RDM reads and write data with a design database as well as reading one or more object oriented…
Method, system, and program product for routing an integrated circuit to be manufactured by sidewall-image transfer
Granted: October 1, 2013
Patent Number:
8549458
Disclosed is a method, apparatus, and program product for routing an electronic design using sidewall image transfer that is correct by construction. The layout is routed by construction to allow successful manufacturing with sidewall image transfer, since the router will not allow a routing configuration in the layout that cannot be successfully manufactured with a two-mask sidewall image transfer. A layout is produced that can be manufactured by a two-mask sidewall image transfer…
Method and system for implementing core placement
Granted: October 1, 2013
Patent Number:
8549457
Disclosed is an improved method, system, and computer program product for performing core placement when presented with an I/O ring design. A multi-pass approach is taken to place and shape core objects into the available core area formed by the inner surface of the I/O ring. The multi-pass approach permits very fast placement of the core objects, which still provides for an accurate estimation of the die size and configuration requirements for the electronic design. Moreover, the…
Method and system for accelerating memory randomization
Granted: October 1, 2013
Patent Number:
8549367
A method and system for randomizing memory in a functional verification test of a user design is disclosed. A random number is generated during the functional verification test. The data stored in the memory of the user design is stored. Encryption keys unique for each memory address of the memory are generated. Each encryption key for each memory address is a function of the random number and the memory address. Data in each memory address of the memory is encrypted with the encryption…
Method and apparatus for thermal analysis of through-silicon via (TSV)
Granted: September 24, 2013
Patent Number:
8543952
Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) design layout. The IC design layout includes several wiring layers in some embodiments. The IC design layout includes a substrate that has at least one through-silicon via (“TSV”). The method divides the IC design layout into a set of elements. The method identifies a temperature distribution for the IC design layout by using the set of elements. In some embodiments,…
Methods, systems, and articles of manufacture for smart pattern capturing and layout fixing
Granted: September 24, 2013
Patent Number:
8543965
Various embodiments are directed at methods and systems for implementing automatic fixing of a layout, implementing fuzzy pattern replacement, and implementing pattern capturing in a layout of an electronic circuit design. Various processes or modules comprise the act or module of identifying a first pattern from within an electronic circuit layout. The processes or modules also comprise identifying a fixing process or a replacement pattern for the first pattern and the act of performing…
Concurrent noise and delay modeling of circuit stages for static timing analysis of integrated circuit designs
Granted: September 24, 2013
Patent Number:
8543954
Systems, apparatus, and methods of static timing analysis for an integrated circuit design in the presence of noise are disclosed. The integrated circuit design undergoing analysis may be partitioned into a plurality of subcircuit stages. Each subcircuit stage in the integrated circuit design may be modeled to include a model of at least one victim driver, at least one aggressor driver, at least one receiver, and an interconnect network. Associated with each subcircuit stage is a set of…
