Method and system for power delivery network analysis
Granted: September 17, 2013
Patent Number:
8539422
The subject application relates to a method and system for power delivery network analysis. The present disclosure is directed towards a computer-implemented method for displaying one or more results of a power delivery network (PDN) analysis associated with an electronic circuit design. The method may include extracting, using at least one processor, an electromagnetic (EM) model for each of one or more discontinuity structures associated with the electronic circuit design. The method…
Methods, systems, and articles of manufacture for creating a hierarchical output for an operation in an electronic design
Granted: September 17, 2013
Patent Number:
8539416
Disclosed are methods, systems, and articles of manufacture for processing a electronic design, which use a computer system to identify an operation associated with a task to be performed on the electronic design, to generate a hierarchical output for multiple shapes for performing the task based at least in part on performing an operation associated with the task, and to display or to store the hierarchical output. The task comprises a dummy fill insertion task or a design verification…
Method and system for implementing top down design and verification of an electronic design
Granted: September 17, 2013
Patent Number:
8539405
Disclosed is a method and system for performing design and verification using stepwise refinement techniques, which can also include or be referred to as “top-down” design verification. With the present stepwise refinement approach, the electronic design can be acted upon at different levels of abstraction, but with approximately the same level of resolution at each abstraction level. A strong relationship of consistency exists between the successive abstraction levels of the design.…
Systems for single pass parallel hierarchical timing closure of integrated circuit designs
Granted: September 17, 2013
Patent Number:
8539402
In one embodiment of the invention, a method includes partitioning an integrated circuit design into a hierarchy of a top level and a plurality of partitions, wherein the top level includes a top level netlist and each partition includes a partition netlist; receiving data path timing budgets and clock path timing budgets for each of the plurality of partitions of the integrated circuit design; and generating a timing budget model of each partition in response to the respective data path…
Method and apparatus for providing user-defined interfaces for a configurable processor
Granted: September 17, 2013
Patent Number:
8539399
A technique that improves both processor performance and associated data bandwidth through user-defined interfaces that can be added to a configurable and extensible microprocessor core. These interfaces can be used to communicate status or control information and to achieve synchronization between the processor and any external device including other processors. These interfaces can also be used to achieve data transfer at the rate of one data element per interface in every clock cycle.…
Annotation management for hierarchical designs of integrated circuits
Granted: September 10, 2013
Patent Number:
8533650
A method is provided to produce a persistent representation of a annotation to a circuit design comprising: providing a block hierarchy that corresponds to the circuit design; displaying in a computer user interface display a first elaborated view of the circuit design that corresponds to the first instance of a block hierarchy; receiving user input to associate the annotation with a component of the elaborated view of the design; providing in a mirrored block hierarchy; and associating…
Multi-CCC current source models and static timing analysis methods for integrated circuit designs
Granted: September 10, 2013
Patent Number:
8533644
In one embodiment of the invention, a multi-CCC current source model is disclosed to perform statistical timing analysis of an integrated circuit design. The multi-CCC current source model includes a voltage waveform transfer function, a voltage dependent current source, and an output capacitor. The voltage waveform transfer function receives an input voltage waveform and transforms it into an intermediate voltage waveform. The voltage dependent current source generates an output current…
Visualization and information display for shapes in displayed graphical images based on user zone of focus
Granted: September 10, 2013
Patent Number:
8533626
Graphical viewing of shapes and descriptive information in displayed graphical images. In one aspect, shape information is displayed in a graphical interface using a computer system and includes causing a display of an image and one or more shapes in the image, and causing a display of a cursor on the display device. Labels are displayed on the display device, each label associated with a different displayed shape. One or more of the labels are displayed within a zone of focus of eyes of…
System and method implementing a simulation acceleration capture buffer
Granted: September 10, 2013
Patent Number:
8532975
A system and method for capturing and delivering emulation data from a hardware emulation system to a simulator running on a host workstation without considerably sacrificing emulation speed or sacrificing the emulation capacity available for a user's logic design. According to one embodiment, a system, comprises a logic software simulator running on a host workstation; a hardware emulation system having a system bus and an emulator chip, the emulator chip includes: an emulation…
Method and system for implementing graphical analysis of hierarchical coverage information using treemaps
Granted: September 3, 2013
Patent Number:
8527936
An improved method, system, user interface, and computer program product is disclosed for performing graphical analysis of coverage. According to some approaches, a graphical user interface uses treemaps to provide analysis of verification coverage. This allows the user to efficiently obtain the overall and/or complete picture of the coverage space, as well as the relative size of nodes in terms of number of coverage elements contained in them. Moreover, the present treemap approach…
Method and system for implementing graphically editable parameterized cells
Granted: September 3, 2013
Patent Number:
8527934
Disclosed is an improved mechanism and method for implementing electronic designs. According to some approaches, a method, mechanism, and compute program product is disclosed for implementing electronic designs that allows visual editing of complex objects with advanced editing features, which also provides for automated correspondence of the editing results to parametric values for a programmable object in the design.
Method and system for optimally connecting interfaces across multiple fabrics
Granted: September 3, 2013
Patent Number:
8527929
A method of connecting an interface to a fabric of an electronic device, the interface having a plurality of nets to be connected to corresponding connectors in the fabric includes associating with each of the connectors in the fabric a first variable indicating that the connector belongs to the interface; associating with each of the connectors in the fabric a second variable indicating a number of higher numbered adjacent connectors for the connector in the interface; connecting each…
Optimizing circuit layouts by configuring rooms for placing devices
Granted: September 3, 2013
Patent Number:
8527928
A computer-readable medium stores a specification for a circuit layout. The specification includes: a configuration of rooms for placing devices, one or more room constraints for the configuration of rooms, one or more groups of devices for the rooms, and one or more device constraints for devices in a same room. The configuration of rooms may include a tree-structure for the rooms. The room constraints may include a common symmetry line for a first room and a second room. The device…
System and method of electron beam writing
Granted: September 3, 2013
Patent Number:
8525135
A system and method for improved electron beam writing that is capable of taking design intent, equipment capability and design requirements into consideration. The system and method determines an optimal writing pattern based, at least in part, on the received information.
Method and mechanism for implementing electronic designs having power information specifications background
Granted: September 3, 2013
Patent Number:
RE44479
A method of adding power control circuitry to a circuit design at each of an RTL and a netlist level comprising: demarcating multiple power domains within the circuit design; specifying multiple power modes each power mode corresponding to a different combination of on/off states of the multiple demarcated power domains; and defining isolation behavior relative to respective power domains.
Detecting indexing errors in declarative languages
Granted: August 27, 2013
Patent Number:
8522210
A computerized method for detecting errors in program code including searching for lines of command codes in the program code, wherein a line of command code includes a set of command codes and a set of indices; separating the sets of command codes from the sets of indices, wherein the sets of indices are a matrix; parsing the sets of command codes to locate three or more consecutive lines of command codes, which have the same sets of command codes; for the three or more consecutive…
Method and system identifying IP blocks and block suppliers for an electronic design
Granted: August 27, 2013
Patent Number:
8522180
An improved approach is described for identifying IP for an electronic design. The present approach can be used to handle situation where there may be difficulties in identifying which, if any, IP matches the desired requirements of an electronic design for which the IP is to be used or integrated. The search wizard of the present approach facilitates identification of IP for an electronic design. Expert systems and expert system services are provided for identifying IP blocks for an…
Method and apparatus for concurrent design of modules across different design entry tools targeted to single simulation
Granted: August 27, 2013
Patent Number:
8521483
A method of generating a representation of an electronic circuit across a plurality of design entry tools includes extracting a first partial circuit including a first plurality of first electronic components from a first partition, extracting a second partial circuit including a second plurality of second electronic components from a second partition, generating a simulation block in the first design entry tool including an interface between the first and second partitions, exporting a…
Method and apparatus for automatically fixing double patterning loop violations
Granted: August 20, 2013
Patent Number:
8516402
A method for automatically decomposing a shape of an IC design layout into two or more shapes in order to resolve a double patterning loop violation involving the shape. The method decomposes the shape by introducing one or more splicing graphs on the shape. These splicing graphs serve as cuts to be made on the shape. By decomposing the shape into several shapes and assigning the shapes to alternating masks for the same layer, the method breaks the double patterning loop. That is, no…
Methods, systems, and articles of manufacture for implementing constraint checking windows for an electronic design for multiple-patterning lithography processes
Granted: August 20, 2013
Patent Number:
8516404
Disclosed are method(s), system(s), and article(s) of manufacture for implementing a layout of an electronic circuit using one or more constraint checking windows. The method identifies some constraints on multiple-patterning lithography and multiple constraint checking windows for the layout. The method determines one or more metrics for a constraint checking window or for a layout and assigns one or more shapes in the one or more constraint checking windows to their respective mask…
