Instruction ordering for in-progress operations
Granted: March 6, 2018
Patent Number:
9910776
Execution of the memory instructions is managed using memory management circuitry including a first cache that stores a plurality of the mappings in the page table, and a second cache that stores entries based on virtual addresses. The memory management circuitry executes operations from the one or more modules, including, in response to a first operation that invalidates at least a first virtual address, selectively ordering each of a plurality of in progress operations that were in…
Packet traffic control in a network processor
Granted: February 27, 2018
Patent Number:
9906468
A network processor controls packet traffic in a network by maintaining a count of pending packets. In the network processor, a pipe identifier (ID) is assigned to each of a number of paths connecting a packet output to respective network interfaces receiving those packets. A corresponding pipe ID is attached to each packet as it is transmitted. A counter employs the pipe ID to maintain a count of packets to be transmitted by a network interface. As a result, the network processor…
Finite automata processing based on a top of stack (TOS) memory
Granted: February 27, 2018
Patent Number:
9904630
A method, and corresponding apparatus and system are provided for optimizing matching of at least one regular expression pattern in an input stream by storing a context for walking a given node, of a plurality of nodes of a given finite automaton of at least one finite automaton, the store including a store determination, based on context state information associated with a first memory, for accessing the first memory and not a second memory or the first memory and the second memory.…
High performance shifter circuit
Granted: February 27, 2018
Patent Number:
9904511
An improved shifter design for high-speed data processors is described. The shifter may include a first stage, in which the input bits are shifted by increments of N bits where N>1, followed by a second stage, in which all bits are shifted by a residual amount. A pre-shift may be removed from an input to the shifter and replaced by a shift adder at the second stage to further increase the speed of the shifter.
Voltage regulator with adaptive bias network
Granted: February 27, 2018
Patent Number:
9904305
A low drop-out voltage regulator includes an error amplifier that generates an amplified error voltage, the error amplifier including a first input for receiving a reference voltage, a second input for receiving a feedback voltage, a bias terminal for receiving an adaptive bias current, and an output. A pass gate providing an output voltage includes a first input connected to a supply voltage and a second input connected to the error amplifier output. A feedback network generating the…
Phantom queue link level load balancing system, method and device
Granted: February 20, 2018
Patent Number:
9900253
A data processing system includes a phantom queue for each of a plurality of output ports each associated with an output link for outputting data. The phantom queues receive/monitor traffic on the respective ports and/or the associated links such that the congestion or traffic volume on the output ports/links is able to be determined by a congestion mapper coupled with the phantom queues. Based on the determined congestion level on each of the ports/links, the congestion mapper selects…
Method and apparatus for improving data integrity using compressed soft information
Granted: January 30, 2018
Patent Number:
9882678
A process capable of employing compression and decompression mechanism to receive and decode soft information is disclosed. The process, in one aspect, is able to receive a data stream formatted with soft information from a communication network such as a wireless network. After identifying a set of bits representing a first logic value from a portion of the data stream in accordance with a predefined soft encoding scheme, the set of bits is compressed into a compressed set of bits. The…
Method and apparatus for parallel and conditional data manipulation in a software-defined network processing engine
Granted: January 30, 2018
Patent Number:
9880844
Embodiments of the present invention relate to fast and conditional data modification and generation in a software-defined network (SDN) processing engine. Modification of multiple inputs and generation of multiple outputs can be performed in parallel. A size of each input or output data can be large, such as in hundreds of bytes. The processing engine includes a control path and a data path. The control path generates instructions for modifying inputs and generating new outputs. The…
Managing buffered communication between cores
Granted: January 16, 2018
Patent Number:
9870328
Communicating among multiple sets of multiples cores includes: buffering messages in first buffer associated with a first set of multiple cores; buffering messages in a second buffer associated with a second set of multiple cores; and transferring messages over communication circuitry from cores not in the first set to the first buffer, and to transferring messages from cores not in the second set to the second buffer. A first core of the first set sends messages corresponding to…
Policer architecture
Granted: January 16, 2018
Patent Number:
9871733
A policer system on one or more place and/or route blocks. The policer system including a plurality of local physical policers each stored in a plurality of physical memory banks and coupled with a plurality of global policers stored in one or more global banks separate from the physical banks. Thus, each bank of the global policers are able to represent a logical combination of a plurality of the physical banks of physical policers.
Algorithm to achieve optimal layout of instruction tables for programmable network devices
Granted: January 16, 2018
Patent Number:
9870204
A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs. The processing network further including an LDE compiler stored on a memory and communicatively coupled with each of the LDEs, wherein the LDE compiler is configured to generate…
Apparatus and method for optimized n-write/1-read port memory design
Granted: January 16, 2018
Patent Number:
9870173
An optimized design of n-write/1-read port memory comprises a memory unit including a plurality of memory banks each having one write port and one read port configured to write data to and read data from the memory banks, respectively. The memory further comprises a plurality of write interfaces configured to carry concurrent write requests to the memory unit for a write operation, wherein the first write request is always presented by its write interface directly to a crossbar, wherein…
Network switching with layer 2 switch coupled co-resident data-plane and network interface controllers
Granted: January 9, 2018
Patent Number:
9866657
A system network switching with layer 2 switch communicatively coupled co-resident data-plane and network interface controllers embodying a method for, receiving a packet from a communication network at the layer 2 switch; parsing the packet; and determining in accordance with a content of the parsed packet whether the packet is to be switched to one of one or more medium access controllers, or one of one or more packet input processors, or one of one or more network interface…
System and method for rule matching in a processor
Granted: January 9, 2018
Patent Number:
9866540
In one embodiment, a system includes a format block configured to receive a key, at least one rule, and rule formatting information. The rule can have one or more dimensions. The format block can be further configured to extract each of the dimensions from the at least one rule. The system can further include a plurality of dimension matching engines (DME). Each DME can be configured to receive the key and a corresponding formatted dimension, and process the key and the corresponding…
Code generator for programmable network devices
Granted: January 9, 2018
Patent Number:
9864584
A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs. The processing network further including an LDE compiler stored on a memory and communicatively coupled with each of the LDEs, wherein the LDE compiler is configured to generate…
Algorithm to derive logic expression to select execution blocks for programmable network devices
Granted: January 9, 2018
Patent Number:
9864583
A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs. The processing network further including an LDE compiler stored on a memory and communicatively coupled with each of the LDEs, wherein the LDE compiler is configured to generate…
Code processor to build orthogonal execution blocks for programmable network devices
Granted: January 9, 2018
Patent Number:
9864582
A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs. The processing network further including an LDE compiler stored on a memory and communicatively coupled with each of the LDEs, wherein the LDE compiler is configured to generate…
Register access control among multiple devices
Granted: January 2, 2018
Patent Number:
9858222
A circuit manages and controls access requests to a register, such as a control and status register (CSR) among a number of devices. In particular, the circuit selectively forwards or suspends off-chip access requests and forwards on-chip access requests independent of the status of off-chip requests. The circuit receives access requests at a plurality of buses, one or more of which can be dedicated to exclusively on-chip requests and/or exclusively off-chip requests. Based on the…
Regex compiler
Granted: January 2, 2018
Patent Number:
9858051
A method and corresponding apparatus relate to converting a nondeterministic finite automata (NFA) graph for a given set of patterns to a deterministic finite automata (DFA) graph having a number of states. Each of the DFA states is mapped to one or more states of the NFA graph. A hash value of the one or more states of the NFA graph mapped to each DFA state is computed. A DFA states table correlates each of the number of DFA states to the hash value of the one or more states of the NFA…
Compiler architecture for programmable application specific integrated circuit based network devices
Granted: December 5, 2017
Patent Number:
9836283
A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs. The processing network further including an LDE compiler stored on a memory and communicatively coupled with each of the LDEs, wherein the LDE compiler is configured to generate…
