Write and read common leveling for 4-bit wide drams
Granted: December 3, 2019
Patent Number:
10497413
System and method of read deskew training for ×4 mode memory control interface configurations. A read deskew training process includes aligning the two strobe signals serving one byte before deskewing the data bits against their corresponding strobe signals. A deskew setting of a variable delay line associated with the second strobe signal is adjusted to align the second strobe signal with reference to the first strobe signal. By aligning the two strobe signals with respect to each…
Methods and apparatus for a unified baseband architecture
Granted: December 3, 2019
Patent Number:
10496329
Methods and apparatus for a unified baseband architecture. In an exemplary embodiment, an apparatus includes a shared memory having a plurality of access ports and a scheduler that outputs scheduled jobs. Each scheduled job identifies data processing to be performed. The apparatus also includes a plurality of functional elements coupled to the plurality of access ports, respectively, to access the shared memory. Each functional element is operable to retrieve selected data from the…
Method and apparatus for using multiple linked memory lists
Granted: November 19, 2019
Patent Number:
10484311
An apparatus and method for queuing data to a memory buffer. The method includes selecting a queue from a plurality of queues; receiving a token of data from the selected queue and requesting, by a queue module, addresses and pointers from a buffer manager for addresses allocated by the buffer manager for storing the token of data. Subsequently, a memory list is accessed by the buffer manager and addresses and pointers are generated to allocated addresses in the memory list which…
Methods and apparatus for providing soft and blind combining for PUSCH acknowledgement (ACK) processing
Granted: November 5, 2019
Patent Number:
10469233
Methods and apparatus for providing soft and blind combining for PUSCH acknowledgement (ACK) processing. In an exemplary embodiment, a method includes soft-combining acknowledgement (ACK) bits received from a UE that are contained in a received sub-frame of symbols. The ACK bits are soft-combined using a plurality of scrambling sequences to generate a plurality of hypothetical soft-combined ACK bit streams. The method also includes receiving a parameter that identifies a selected…
Compiler architecture for programmable application specific integrated circuit based network devices
Granted: November 5, 2019
Patent Number:
10466976
A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs. The processing network further including an LDE compiler stored on a memory and communicatively coupled with each of the LDEs, wherein the LDE compiler is configured to generate…
Engine architecture for processing finite automata
Granted: November 5, 2019
Patent Number:
10466964
An engine architecture for processing finite automata includes a hyper non-deterministic automata (HNA) processor specialized for non-deterministic finite automata (NFA) processing. The HNA processor includes a plurality of super-clusters and an HNA scheduler. Each super-cluster includes a plurality of clusters. Each cluster of the plurality of clusters includes a plurality of HNA processing units (HPUs). A corresponding plurality of HPUs of a corresponding plurality of clusters of at…
Serializer/deserializer (SerDes) lanes with lane-by-lane datarate independence
Granted: October 29, 2019
Patent Number:
10461917
A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane. The multiple SerDes data lanes may operate at data rates independent from one another. A single low frequency clock is input to the PHY. A frequency of the single low frequency clock is increased via a common integer-N phase-locked loop (PLL) on the PHY to produce a higher…
Scope in decision trees
Granted: October 29, 2019
Patent Number:
10460250
A root node of a decision tree data structure may cover all values of a search space used for packet classification. The search space may include a plurality of rules, the plurality of rules having at least one field. The decision tree data structure may include a plurality of nodes, the plurality of nodes including a subset of the plurality of rules. Scope in the decision tree data structure may be based on comparing a portion of the search space covered by a node to a portion of the…
Method and apparatus for port access management at a distributed job manager in a digital multi-processor system
Granted: October 29, 2019
Patent Number:
10459770
A method and a system for port access management at a distributed job manager, encompassing: initializing a port access process for each of one or more ports on a processing device; determining first whether a job is assigned to an active slot identified by an active_slot_id on the processing device, and when the determining is positive: determining second whether the job has been serviced by a port identified by the active_slot_id; and when either the first determining is negative or…
Methods and apparatus for control channel detection in an uplink shared channel
Granted: October 15, 2019
Patent Number:
10448377
Methods and apparatus for channel detection in an uplink shared control channel. In an exemplary embodiment, a method includes generating soft-combined bit streams for an acknowledgement (ACK) indicator, rank indicator (RI), and channel quality indicator (CQI) received in an uplink shared channel. The method also includes decoding the ACK, RI, and CQI soft-combined bit streams to generate Top-M decoded bit streams for each indicator, and generating Top-Q symbols for each indicator from…
Managing lock and unlock operations using traffic prioritization
Granted: October 15, 2019
Patent Number:
10445096
Managing lock and unlock operations for a first thread executing on a first processor core includes, for each instruction included in the first thread and identified as being associated with: (1) a lock operation corresponding to a particular lock, in response to determining that the particular lock has already been acquired, continuing to perform the lock operation for multiple attempts during which the first processor core is not able to execute threads other than the first thread, or…
Apparatus and method for collecting responses to a plurality of parallel lookup queries from a flow of packets at a network switch
Granted: October 1, 2019
Patent Number:
10430472
A network lookup engine in a network switch is configured to generate multiple lookup queries for each incoming packet in parallel to a remote search engine. The number and type of the lookup queries depend on the protocols supported by the network switch. The responses from the search engine arriving at the lookup engine are not in the same order as the order of the packets. The network lookup engine is configured to collect the responses for the parallel lookup queries in two modes: 1)…
Systems and methods for perfect forward secrecy (PFS) traffic monitoring via a hardware security module
Granted: September 24, 2019
Patent Number:
10425234
A new approach is proposed to support monitoring Perfect Forward Secrecy (PFS) network traffic by utilizing a hardware security module (HSM) appliance. Here, the HSM appliance is a high-performance, Federal Information Processing Standards (FIPS) 140-compliant security hardware with embedded firmware, which can be used for management and sharing of ephemeral keys used in a secured PFS communication session between two parties. Specifically, the HSM allows a server to share one or more of…
Methods and apparatus for adaptive power profiling in a baseband processing system
Granted: September 24, 2019
Patent Number:
10423215
Methods and apparatus for adaptive power profiling in a baseband processing system. In an exemplary embodiment, an apparatus includes one or more processing engines. Each processing engine performs at least one data processing function. The apparatus also includes an adaptive power profile (APP) and a job manager that receives job requests for data processing. The job manager allocates the data processing associated with the job requests to the processing engines based on the adaptive…
Packet processor forwarding database cache
Granted: September 17, 2019
Patent Number:
10419571
A forwarding database cache system is described herein. The forwarding database cache system includes a main forwarding database and one or more forwarding database caches. When a packet is received, the cache is searched first for information such as address information, and if found, then the packet is forwarded to the appropriate destination. If the address information is not found in the cache, then the main forwarding database is searched, and the packet is forwarded to the…
Methods and systems for overlapping protection domain in network devices
Granted: September 17, 2019
Patent Number:
10419481
Methods and systems for securing data are provided. For example, one method includes receiving at an adapter, data with a first type of error protection code from a host memory of a computing device; adding by the adapter a second type of error protection code to the data before removing the first type of error protection code; generating by the adapter, a frame header for the data with a protocol specific protection code and a third type of error protection code, where the third type of…
Session based packet mirroring in a network ASIC
Granted: September 17, 2019
Patent Number:
10417067
A forwarding pipeline of a forwarding engine includes a mirror bit mask vector with one bit per supported independent mirror session. Each bit in the mirror bit mask vector can be set at any point in the forwarding pipeline when the forwarding engine determines that conditions for a corresponding mirror session are met. At the end of the forwarding pipeline, if any of the bits in the mirror bit mask vector is set, then a packet, the mirror bit mask vector and a pointer to the start of a…
Systems and methods for text analytics processor
Granted: September 10, 2019
Patent Number:
10409911
A hardware-based programmable text analytics processor has a plurality of components including at least a tokenizer, a tagger, a parser, and a classifier. The tokenizer processes an input stream of unstructured text data and identifies a sequence of tokens along with their associated token ids. The tagger assigns a tag to each of the sequence of tokens from the tokenizer using a trained machine learning model. The parser parses the tagged tokens from the tagger and creates a parse tree…
Multiple ethernet ports and port types using a shared data path
Granted: September 3, 2019
Patent Number:
10404623
In an embodiment an interface unit includes a transmit pipeline configured to transmit egress data, and a receive pipeline configured to receive ingress data. At least one of the transmit pipeline and the receive pipeline being may be configured to provide shared resources to a plurality of ports. The shared resources may include at least one of a data path resource and a control logic resource.
Distributed interrupt scheme in a multi-processor system
Granted: August 27, 2019
Patent Number:
10394730
Methods and systems are disclosed for routing and distributing interrupts in a multi-processor computer to various processing elements within the computer. A system for distributing the interrupts may include a plurality of logic devices configured in a hierarchical tree structure that distributes incoming interrupts to interrupt redistributors (redistribution devices). The system also includes plural processing elements, where each processing element has an associated bus address. A…
