Method of identifying internal destinations of network packets and an apparatus thereof
Granted: August 27, 2019
Patent Number:
10397113
Embodiments of the apparatus of identifying internal destinations of network packets relate to a network chip that allows flexibility in handling packets. The handling of packets can be a function of what the packet contents are or where the packets are from. The handling of packets can also be a function of both what the packet contents are and where the packets are from. In some embodiments, where the packets are from refers to unique port numbers of chip ports that the packets arrived…
Methods and apparatus for calculating transport block (TB) cyclic redundancy ceck (CRC) values
Granted: August 20, 2019
Patent Number:
10389481
In an exemplary embodiment, a method for calculating transport block (TB) cyclic redundancy check (CRC) values includes receiving code blocks (CBs) that form code block groups (CBGs), which form a TB, generating partial TB CRC values from the CBGs, and processing the partial TB CRC values to determine a full TB CRC value. The method also includes comparing the full TB CRC value to a received TB CRC value to determine if the TB has been successfully received. An apparatus includes a…
Method and apparatus for coordinated multipoint receiver processing acceleration and latency reduction
Granted: July 23, 2019
Patent Number:
10362498
Methods and apparatus for coordinated multipoint receiver processing acceleration and latency reduction. In an exemplary embodiment, an apparatus includes a receiver that receives symbols from a wireless transmission and stores the symbols in a memory. The receiver also outputs an indicator that indicates that storage of the symbols in the memory has begun. The apparatus also includes a controller that outputs control signaling in response to the indicator. The apparatus also includes a…
Methods and apparatus for twiddle factor generation for use with a programmable mixed-radix DFT/IDFT processor
Granted: July 9, 2019
Patent Number:
10349251
Twiddle factor generation for use with a programmable mix-radix vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values. In an exemplary embodiment, an apparatus includes look-up table logic that receives twiddle control factors and outputs a selected twiddle factor scaler value (TFSV), a base vector generator that generates a base vector values based on the selected TFSV, and a twiddle column generator that generates a twiddle vector from…
Fast hardware switchover in a control path in a network ASIC
Granted: July 2, 2019
Patent Number:
10341130
A multicast destination table contains a list of links. The list of links includes the main link that is currently in use and alternate links to reach the same destination. The links in the list of links are ordered based on a metric. Each of the links is stored as an entry in the multicast destination table. A multicast replication engine traverses the list of links until an enabled link in the list of links is reached, and replicates a packet according to data associated with the…
Instruction ordering for in-progress operations
Granted: July 2, 2019
Patent Number:
10339054
Execution of the memory instructions is managed using memory management circuitry including a first cache that stores a plurality of the mappings in the page table, and a second cache that stores entries based on virtual addresses. The memory management circuitry executes operations from the one or more modules, including, in response to a first operation that invalidates at least a first virtual address, selectively ordering each of a plurality of in progress operations that were in…
Managing fairness for lock and unlock operations using operation prioritization
Granted: June 25, 2019
Patent Number:
10331500
Managing lock and unlock operations for a first thread executing on a first processor core includes, for each instruction included in the first thread and identified as being associated with: (1) a lock operation corresponding to a particular lock stored in a particular memory location, in response to determining that the particular lock has already been acquired, continuing to perform the lock operation for multiple attempts using associated operation messages for accessing the…
Baseline wander compensation
Granted: June 4, 2019
Patent Number:
10312920
A data recovery circuit provides compensation for baseline wander exhibited by a data signal. An adaptive equalizer generates a recovered data signal from a data input. A level shifter and low-pass filter provide a compensation signal as a function of the recovered data signal. An adaptation engine adjusts the level of the compensation signal to compensate for baseline wander. The adaptive equalizer generates the recovered data signal as a function of the data input and the compensation…
Methods and apparatus for a vector subsystem for use with a programmable mixed-radix DFT/IDFT processor
Granted: June 4, 2019
Patent Number:
10311018
A vector memory subsystem for use with a programmable mix-radix vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values. In an exemplary embodiment, an apparatus includes a vector memory bank and a vector memory system (VMS) that generates input memory addresses that are used to store input data into the vector memory bank. The VMS also generates output memory addresses that are used to unload vector data from the memory banks. The input…
Approach for chip-level flop insertion and verification based on logic interface definition
Granted: May 28, 2019
Patent Number:
10303626
Systems and methods for inserting flops at the chip-level to produce a signal delay for preventing buffer overflow are disclosed herein. Shells of modules described in an RTL description and their connections are analyzed to determine a signal latency between a sender block and a receiver block. The logical interfaces of the shells are grouped in a structured document with associated rules. Flops are inserted between the sender block and the receiver block to introduce a flop delay to…
Sharing resources in a multi-context computing system
Granted: May 28, 2019
Patent Number:
10303514
In an embodiment, a method of providing quality of service (QoS) to at least one resource of a hardware processor includes providing, in a memory of the hardware processor, a context including at least one quality of service parameter and allocating access to the at least one resource of the hardware processor based on the quality of service parameter of the context, a device identifier, a virtual machine identifier, and the context.
Method and apparatus for performing a weighted queue scheduling using a set of fairness factors
Granted: May 14, 2019
Patent Number:
10291540
A computer-implemented medium using a scheduler for processing requests by receiving packet data from multiple source ports and then classifying, the received packet data based upon the source port received and a destination port the data being sent. Next, sorting, the classified packet data into multiple queues in a buffer, and updating, a static component of one or more of the multiple queues upon the queue receiving the sorted classified data packet. Further, scheduling, using the…
Serializer/deserializer (SerDes) lanes with lane-by-lane datarate independence
Granted: May 14, 2019
Patent Number:
10291386
A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane. The multiple SerDes data lanes may operate at data rates independent from one another. A single low frequency clock is input to the PHY. A frequency of the single low frequency clock is increased via a common integer-N phase-locked loop (PLL) on the PHY to produce a higher…
Packet processing system, method and device utilizing a port client chain
Granted: May 14, 2019
Patent Number:
10289575
A packet processing system having each of a plurality of hierarchical clients and a packet memory arbiter serially communicatively coupled together via a plurality of primary interfaces thereby forming a unidirectional client chain. This chain is then able to be utilized by all of the hierarchical clients to write the packet data to or read the packet data from the packet memory.
Methods and systems for distribution of packets among parsing clusters
Granted: May 7, 2019
Patent Number:
10284690
A method for parsing network packets via one or more clusters configured to parse network packets comprises receiving one or more packets to be parsed; determining a candidate cluster of the one or more clusters for parsing the one or more packets; transmitting the one or more packets to the candidate cluster; launching the candidate cluster to parse the one or more packets when a launch condition is met; and receiving parse results for the one or more packets from the candidate cluster.…
Software assisted hardware configuration for software defined network system-on-chip
Granted: May 7, 2019
Patent Number:
10282315
A software and hardware co-validation for SDN SoC method and system are able to be used to test software and hardware using PCIe (or another implementation) utilizing sockets and messages as the communication medium. An entire software stack as well as hardware are able to be tested. Additionally, multiple chips (SoCs) are able to be programmed at the same time, not just one, as in previous implementations.
Managing cache partitions based on cache usage information
Granted: May 7, 2019
Patent Number:
10282299
Partition information includes entries that each include an entity identifier and associated cache configuration information. A controller manages memory requests originating from processor cores, including: comparing at least a portion of an address included in a memory request with tags stored in a cache to determine whether the memory request results in a hit or a miss, and comparing an entity identifier included in the memory request with stored entity identifiers to determine a…
System and method for storing lookup request rules in multiple memories
Granted: April 30, 2019
Patent Number:
10277510
In one embodiment, a system includes a data navigation unit configured to navigate through a data structure stored in a first memory to a first representation of at least one rule. The system further includes at least one rule processing unit configured to a) receive the at least one rule based on the first representation of the at least one rule from a second memory to one of the rule processing unit, and b) processing a key using the at least one rule.
Methods and systems for message logging and retrieval in computer systems
Granted: April 30, 2019
Patent Number:
10275261
Methods and systems for a computing device and an adapter are provided. One method includes allocating a memory location at the adapter for storing messages logged by a driver during a pre-boot operation of an operating system of the computing device coupled to the driver; generating a variable by the driver executed by the computing device, the variable includes an address of the memory location and is identified by a unique identifier; using a first application programming interface…
Signal presence detection circuit and method
Granted: April 16, 2019
Patent Number:
10263759
In some embodiments, the circuits (and methods) may include a reference generator configured to generate a reference signal. The circuits (and methods) may also include a signal presence detection module configured to perform calibration on itself, during a calibration phase, based upon the reference signal. The signal presence detection module may be further configured to receive an input signal. The signal presence detection module may be further configured to perform detection, during…
