Systems and methods for offloading IPSEC processing to an embedded networking device
Granted: April 2, 2019
Patent Number:
10250571
A new approach is proposed that contemplates systems and methods to support a mechanism to offload IPSec/IKE processing of virtual machines (VMs) running on a host to an embedded networking device, which serves as a hardware accelerator for the VMs that need to have secured communication with a remote device/server over a network. By utilizing a plurality of its software and hardware features, the embedded networking device is configured to perform all offloaded IPSec operations on data…
Managing lock and unlock operations using active spinning
Granted: April 2, 2019
Patent Number:
10248420
Managing instructions on a processor includes: executing threads having access to a stored library of operations. For a first thread executing on the first processor core, for each instruction included in the first thread and identified as being associated with a lock operation corresponding to a particular lock, the managing includes determining if the particular lock has already been acquired for another thread executing on a processor core other than the first processor core, and if…
Method and apparatus for dynamic virtual system on chip
Granted: March 19, 2019
Patent Number:
10235211
A processor device comprises a plurality of virtual systems on chip, configured to utilize resources of a plurality of resources in accordance with a resource alignment between the plurality of virtual systems on chip and the plurality of resources. The processor device may further comprises a resource aligning unit configured to modify the resource alignment, dynamically, responsive to at least one event. Modifying the resource alignment, dynamically, may prevent a loss in throughput…
Frequency divider
Granted: March 12, 2019
Patent Number:
10230381
A frequency divider circuit comprises a first divider chain including at least one first divider cell and a second divider chain coupled to the first divider chain to form an extendable divider chain. The second divider chain includes at least one second divider cell with a respective reset control. An effective length of the extendable divider chain may be altered, dynamically, via the respective reset control. Altering the effective length, dynamically, enables a division ratio of the…
NSP manager
Granted: March 12, 2019
Patent Number:
10229144
In an embodiment, a method of updating a memory with a plurality of memory lines, the memory storing a tree, a plurality of buckets, and a plurality of rules, can include maintaining a copy of the memory with a plurality of memory lines. The method can further include writing a plurality of changes to at least one of the tree, the plurality of buckets, and the plurality of rules to the copy. The method can additionally include determining whether each of the plurality of changes is an…
Incremental update heuristics
Granted: March 12, 2019
Patent Number:
10229139
A system, apparatus, and method are provided for receiving one or more incremental updates including adding, deleting, or modifying rules of a Rule Compiled Data Structure (RCDS) used for packet classification. Embodiments disclosed herein may employ at least one heuristic for maintaining quality of the RCDS. At a given one of the one or more incremental updates received, a section of the RCDS may be identified and recompilation of the identified section may be triggered, altering the…
Managing virtual-address caches for multiple memory page sizes
Granted: March 5, 2019
Patent Number:
10223279
A translation lookaside buffer stores information indicating respective page sizes for different translations. A virtual-address cache module manages entries, where each entry stores a memory block in association with a virtual address and a code representing at least one page size of a memory page on which the memory block is located. The managing includes: receiving a translation lookaside buffer invalidation instruction for invalidating at least one translation lookaside buffer entry…
Method and circuit for low voltage current-mode bandgap
Granted: March 5, 2019
Patent Number:
10222817
A bandgap reference (BGR) circuit and method generates a constant voltage reference that is stable over temperature variations. The BGR circuit is composed of a proportional to absolute temperature (PTAT) stage, a complementary to absolute temperature (CTAT) stage, and an output stage interposed between the PTAT stage and the CTAT stage. The PTAT stage is configured to produce a PTAT current and the CTAT stage is configured to produce a CTAT current. The BGR circuit is configured to…
Method and apparatus for table aging in a network switch
Granted: February 26, 2019
Patent Number:
10216780
Embodiments of the present invention relate to a centralized table aging module that efficiently and flexibly utilizes an embedded memory resource, and that enables and facilitates separate network controllers. The centralized table aging module performs aging of tables in parallel using the embedded memory resource. The table aging module performs an age marking process and an age refreshing process. The memory resource includes age mark memory and age mask memory. Age marking is…
Apparatus and method for scalable and flexible access control list lookup in a network switch
Granted: February 26, 2019
Patent Number:
10218643
A network switch to support scalable and flexible access control list (ACL) lookup comprises a packet processing pipeline including a plurality of packet processing units each configured to generate a master key for an ACL lookup request to a memory pool and process a received packet based on ACL search results. The network switch further includes said memory pool including a plurality of memory groups each configured to maintain a plurality of ACL tables to be searched in one or more…
Caching methods and systems using a network interface card
Granted: February 26, 2019
Patent Number:
10216666
A computing device having a host memory and a host processor for executing instructions out of the host memory; and a network interface card interfacing with the computing device are provided. When there is a cache hit for a read request, the network interface card processes the read request by obtaining data stored from one or both of the host memory and a storage device that the network interface card accesses without involving the host processor and when there are is a cache miss,…
Local ordering of instructions in a computing system
Granted: February 26, 2019
Patent Number:
10216430
A method for managing an observed order of instructions in a computing system includes utilizing an overloaded memory barrier instruction to specify whether a global ordering constraint or a local ordering constraint is enforced.
Methods and apparatus for providing a programmable mixed-radix DFT/IDFT processor using vector engines
Granted: February 19, 2019
Patent Number:
10210135
A programmable vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values is disclosed. In an exemplary embodiment, an apparatus includes a memory bank and a vector data path pipeline coupled to the memory bank. The apparatus also includes a configurable mixed radix engine coupled to the vector data path pipeline. The configurable mixed radix engine is configurable to perform a selected radix computation selected from a plurality of radix…
Hierarchical hardware linked list approach for multicast replication engine in a network ASIC
Granted: February 12, 2019
Patent Number:
10205649
A multicast rule is represented in a hierarchical linked list with N tiers. Each tier or level in the hierarchical linked list corresponds to a network layer of a network stack that requires replication. Redundant groups in each tier are eliminated such that the groups in each tier are stored exactly once in a replication table. A multicast replication engine traverses the hierarchical linked list and replicates a packet according to each node in the hierarchical linked list.
Baseboard interconnection device, system and method
Granted: February 5, 2019
Patent Number:
10198389
An information processing system, device and method wherein a base board is configured to couple to both back and midplane systems as well as optical modules for use in a data center rack system. Specifically, a base board adapter is configured to electrically couple to an integrated backplane/midplane electronic interface of the base board and translate the signals to one or more optical interface module connectors such that one or more optical interface modules are able to be coupled…
Methods and apparatus for frequency offset estimation
Granted: January 1, 2019
Patent Number:
10171278
Methods and apparatus for frequency offset estimation are disclosed. In an exemplary embodiment, a method includes determining a demodulation reference signal (DMRS) frequency offset estimate from DMRS symbols in a received signal, and determining a cyclic prefix (CP) frequency offset estimate from cyclic prefix values in the received signal. The method also includes combining the DMRS and CP frequency offset estimates to determine a final frequency offset estimate. In an exemplary…
Methods and apparatus for control bit detection
Granted: January 1, 2019
Patent Number:
10171207
Methods and apparatus for control bit detection. In an exemplary embodiment, a method includes receiving an LLR sequence (l) that includes P control bits and calculating a sum of LLR squares parameter (L) associated with the LLR sequence. The method also includes generating a value (Vp) for each of the 2P combination of the control bits. Each Vp value is based on a parameter sequence and the LLR sequence. The method also includes determining a smallest value of Vp, and outputting a…
Method for work scheduling in a multi-chip system
Granted: January 1, 2019
Patent Number:
10169080
According to at least one example embodiment, a multi-chip system includes multiple chip devices configured to communicate to each other and share hardware resources. According to at least one example embodiment, a method of processing work item in the multi-chip system comprises designating, by a work source component associated with a chip device, referred to as the source chip device, of the multiple chip devices, a work item to a scheduler for scheduling. The scheduler then assigns…
Duty cycle correction method
Granted: December 18, 2018
Patent Number:
10158353
The present disclosure includes circuits and methods that adjust and correct duty cycles of circuits. The circuits and methods receive a signal from a first circuit and forward the received signal to a second circuit that retrieves a first setting (X) that provides a measure of duty cycle of the received signal. The circuits and methods then invert the received signal, retrain the second circuit based upon the inverted received signal, and retrieve a second setting (Y) of the retrained…
Method and apparatus for managing global chip power on a multicore system on chip
Granted: December 11, 2018
Patent Number:
10152102
According to at least one example embodiment, a method and corresponding apparatus for controlling power in a multi-core processor chip include: accumulating, at a controller within the multi-core processor chip, one or more power estimates associated with multiple core processors within the multi-core processor chip. A global power threshold is determined based on a cumulative power estimate, the cumulative power estimate being determined based at least in part on the one or more power…
