Method and apparatus for a virtual system on chip
Granted: December 4, 2018
Patent Number:
10146463
A virtual system on chip (VSoC) is an implementation of a machine that allows for sharing of underlying physical machine resources between different virtual systems. A method or corresponding apparatus of the present invention relates to a method that includes a plurality of virtual systems on chip and a configuring unit. The configuring unit is arranged to configure resources on the method for the plurality of virtual systems on chip as a function of an identification tag assigned to…
Modular serializer and deserializer
Granted: November 27, 2018
Patent Number:
10141949
Modular serializer and deserializer circuits convert a data input in a variety of applications. The serializer includes an array of cells that receive a parallel data input and transfer the word, row by row, to an output buffer that generates a corresponding serial data output. The deserializer includes an input buffer that receives a serial data input and transfers partial words sequentially through an array of cells. When the word fully occupies the cells, the array transmits the word…
Methods and apparatus for providing an FFT engine using a reconfigurable single delay feedback architecture
Granted: November 27, 2018
Patent Number:
10140250
Methods and apparatus for providing an FFT engine using a reconfigurable single delay feedback architecture. In one aspect, an apparatus includes a radix-2 (R2) single delay feedback (SDF) stage that generates a radix-2 output and a radix-3 (R3) SDF stage that generates a radix-3 output. The apparatus also includes one or more radix-2 squared (R2^2) SDF stages that generate a radix-4 output. The apparatus further includes a controller that configures a sequence of radix stages selected…
Methods and systems for securing data stored at a storage area network
Granted: November 13, 2018
Patent Number:
10129219
Methods and systems for securing data are provided. For example, one method includes providing context information for an input/output (I/O) operation to a security module by an adapter communicating with a computing device and a storage device via a network; storing encryption parameters associated to a security association handle by the security module; using a workflow handle by the security module to obtain the security association handle for retrieving stored encryption parameters…
Systems and methods for defining storage
Granted: November 13, 2018
Patent Number:
10129162
System and methods are provided for providing modular control of network data packet handling and configurations. In one aspect, a storage-to-network mapping data structure is provided that can translate network connection parameters into high level, searchable concepts. In turn, these searchable concepts can be used by one or more modular software-defined storage applications to provide rules for network traffic handling that can then be merged into a dataplane forwarding data structure…
Network switching with co-resident data-plane and network interface controllers
Granted: October 30, 2018
Patent Number:
10116772
A system with co-resident data-plane and network interface controllers embodying a method for network switching of a data packet incoming from a network at a packet input processor portion of a network interface resource comprising the packet input processor, a packet output processor, and a network interface controller, implemented on a chip, to a target entity, is disclosed. Additionally, the system embodying a method for network switching of a data packet outgoing from an internal…
Hybrid wildcard match table
Granted: October 30, 2018
Patent Number:
10116564
Embodiments of the present invention are directed to a wildcard matching solution that uses a combination of static random access memories (SRAMs) and ternary content addressable memories (TCAMs) in a hybrid solution. In particular, the wildcard matching solution uses a plurality of SRAM pools for lookup and a spillover TCAM pool for unresolved hash conflicts.
Methods and apparatus for providing a programmable mixed-radix DFT/IDFT processor using vector engines
Granted: October 30, 2018
Patent Number:
10114797
A programmable vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values is disclosed. In an exemplary embodiment, an apparatus includes a memory bank and a vector data path pipeline coupled to the memory bank. The apparatus also includes a configurable mixed radix engine coupled to the vector data path pipeline. The configurable mixed radix engine is configurable to perform a selected radix computation selected from a plurality of radix…
Packet scheduling using hierarchical scheduling process
Granted: October 23, 2018
Patent Number:
10110515
System and method of data routing according to a hierarchical scheduling process. Incoming data traffic is allocated to various queues of a buffer. A scheduling tree has a top level for queues, a bottom level for egress ports, and a plurality of intermediate levels corresponding to different granularities with respect to service categories. Each queue is assigned to a particular node in each intermediate level of the scheduling tree. The scheduling tree traverses through multiple…
Processing of finite automata based on memory hierarchy
Granted: October 23, 2018
Patent Number:
10110558
At least one processor may be operatively coupled to a plurality of memories and a node cache and configured to walk nodes of a per-pattern non-deterministic finite automaton (NFA). Nodes of the per-pattern NFA may be stored amongst one or more of the plurality of memories based on a node distribution determined as a function of hierarchical levels mapped to the plurality of memories and per-pattern NFA storage allocation settings configured for the hierarchical levels, optimizing run…
Protocol switching over multi-network interface
Granted: October 23, 2018
Patent Number:
10110393
This application is directed to protocol switching over multi-network interface, specifically switching between mirroring and streaming protocols using one L2 connection established between a source multimedia device and a sink multimedia device, depending on the application and/or multimedia content and as facilitated by a controller device.
Phantom queue link level load balancing system, method and device
Granted: October 16, 2018
Patent Number:
10103993
A data processing system includes a phantom queue for each of a plurality of output ports each associated with an output link for outputting data. The phantom queues receive/monitor traffic on the respective ports and/or the associated links such that the congestion or traffic volume on the output ports/links is able to be determined by a congestion mapper coupled with the phantom queues. Based on the determined congestion level on each of the ports/links, the congestion mapper selects…
Systems and methods for offloading inline SSL processing to an embedded networking device
Granted: October 9, 2018
Patent Number:
10095558
A new approach is proposed that contemplates systems and methods to support a mechanism to offload all aspects of inline SSL processing of an application running on a server/host to an embedded networking device such as a Network Interface Card (NIC), which serves as a hardware accelerator for all applications running on the server that need to have a secure connection with a remote client device over a network. By utilizing a plurality of its software and hardware features, the embedded…
Apparatus and method for scalable and flexible wildcard matching in a network switch
Granted: October 2, 2018
Patent Number:
10091137
A network switch to support scalable and flexible wildcard matching (WCM) comprises a packet processing pipeline including a plurality of packet processing units each configured to generate a master key for a WCM request to a memory pool and process a packet based on looked up WCM rules. The memory pool includes a plurality of memory groups each configured to maintain a plurality of WCM tables to be searched in one or more SRAM memory tiles of the memory group, format the master key…
Systems and methods for hardware accelerated metering for openflow protocol
Granted: September 25, 2018
Patent Number:
10084719
A new approach is proposed that contemplates systems and methods to support hardware-based Quality of Service (QoS) operations, which offloads metering functionalities under OpenFlow protocol to a programmable hardware unit/block/component. The hardware unit supports several hardware implemented ports and each port supports multiple configurable queues for the packet flows through a network switch/chip/system. Specifically, the hardware unit includes a plurality of descriptor queues…
Batch incremental update
Granted: September 25, 2018
Patent Number:
10083200
A system, apparatus, and method are provided for adding, deleting, and modifying rules in one update from the perspective of an active search process for packet classification. While a search processor searches for one or more rules that match keys generated from received packets, there is a need to add, delete, or modify rules. By organizing a plurality incremental updates for adding, deleting, or modifying rules into a batch update, several operations for incorporating the incremental…
Testbench builder, system, device and method
Granted: September 25, 2018
Patent Number:
10082538
A testbench for testing a device under test (DUT), wherein the testbench has a verification environment including a reference model, a scoreboard and a customized agent for each interface that the DUT needs to receive input from and/or transmit output on. The testbench system is able to be generated by a testbench builder that automatically creates a scoreboard, a reference model, a dispatcher and generic agents including generic drivers, loopback ports, sequencers and/or generic…
Multiple-interrupt propagation scheme in a network ASIC
Granted: September 18, 2018
Patent Number:
10078605
Embodiments of the present invention are directed to a multiple-interrupt propagation scheme, which is an automated mechanism for the specification and creation of interrupts. Interrupts originating at leaf nodes of a network chip are categorized into different service levels according to their interrupt types and are propagated to a master of the network chip via a manager. For each interrupt, depending on its service level, the manager either instantaneously propagates the interrupt or…
Approach for interfacing a pipeline with two or more interfaces in a processor
Granted: September 18, 2018
Patent Number:
10078601
In an embodiment, interfacing a pipeline with two or more interfaces in a hardware processor includes providing a single pipeline in a hardware processor. The single pipeline presents at least two visible units. The single pipeline includes replicated architecturally visible structures, shared logic resources, and shared architecturally hidden structures. The method further includes receiving a request from one of a plurality of interfaces at one of the visible units. The method also…
Packet processing system, method and device utilizing memory sharing
Granted: August 28, 2018
Patent Number:
10061513
A packet processing system having a control path memory of a control path subsystem and a datapath memory of a datapath subsystem. The datapath subsystem stores packet data of incoming packets and the control path subsystem performs matches of a subset of packet data, or a hash of the packet data, against the contents of a the control path memory in order to process the packets. The packet processing system enabling a portion of the datapath memory to be used by the control subsystem if…
