Management of an over-subscribed shared buffer
Granted: August 14, 2018
Patent Number:
10050896
A method of managing a buffer (or buffer memory) includes utilizing one or more shared pool buffers, one or more port/priority buffers and a global multicast pool. When packets are received, a shared pool buffer is utilized; however, if a packet does not fit in the shared pool buffer, then the appropriate port/priority buffer is used. If the packet is a multicast packet, then the global multicast pool is utilized for copies of the packet.
Method of reducing latency in a flexible parser and an apparatus thereof
Granted: August 14, 2018
Patent Number:
10050833
Embodiments of the apparatus for reducing latency in a flexible parser relate to an implementation that optimizes each parser engine within the parser. A packet enters the parser. Each of the parser engines processes the packet if processing is required. Otherwise, the parser engine simply forwards the packet through without processing the packet, thereby reducing latency. Each parser engine includes a memory. The memory stores bypass data and status information that indicates whether…
Process-compensated level-up shifter circuit
Granted: August 14, 2018
Patent Number:
10050624
A level-up shifter circuit is suitable for high speed and low power applications. The circuit dissipates almost no static power, or leakage current, compared to conventional designs and can preserve the signal's duty cycle even at high data rates. This circuit can be used with a wide range of power supplies while maintaining operational integrity, and includes circuitry to compensate for process variations.
Collapsed address translation with multiple page sizes
Granted: August 7, 2018
Patent Number:
10042778
A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The…
Hierarchical statisically multiplexed counters and a method thereof
Granted: July 31, 2018
Patent Number:
10038448
Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life.…
Methods and apparatus for providing soft and blind combining for PUSCH CQI processing
Granted: July 17, 2018
Patent Number:
10027457
Methods and apparatuses for providing soft and blind combining for PUSCH CQI processing are disclosed. In an exemplary embodiment, a method includes generating a plurality of hypothetical rank indicator (RI) values associated with a user equipment (UE), and concurrently soft-combining channel quality information (CQI) and RI information associated with the UE that is contained in a received subframe of symbols. The RI information is soft-combined to generate a soft-combined RI bit stream…
Systems and methods for offloading link aggregation to a host bus adapter (HBA) in single root I/O virtualization (SRIOV) mode
Granted: July 17, 2018
Patent Number:
10025740
A new approach is proposed to offload of link aggregation from a host to a HBA in SRIOV mode. The HBA first creates one or more link aggregation offload engines each having one or more physical ports and to establish a first link between a VM running on the host and one of the link aggregation offload engines for network data transmission with the VM. Once a data packet is received from the VM over the first link, the link aggregation offload engine chooses a first physical port based on…
Methods and systems for data alignment in network devices
Granted: July 10, 2018
Patent Number:
10020929
Methods and systems for network devices are provided. One method includes receiving a serial data stream at a network interface of a network device coupled to a network link to communicate with other networked devices, the data stream including an alignment marker with a bit pattern for recovering a bit stream used by network device logic for processing the received serial data stream; using a plurality of comparators for simultaneously comparing within a single clock cycle, portions of…
Method and system for processing write requests
Granted: July 10, 2018
Patent Number:
10019203
Machine implemented methods and systems for writing data at a storage device are provided. A write command from an initiator adapter is received at a target adapter interfacing with a target controller for writing data to the storage device; where the write command includes information regarding a virtual logical unit number (LUN) for writing data in response to the write command. The target controller uses an indicator to notify the target adapter to process the write command and…
Programmable validation of transaction requests
Granted: July 3, 2018
Patent Number:
10013385
A data processor includes an input/output bridge that provides enforcement of a security status on transactions between devices across the bridge. The bridge includes circuitry to parse a received request to obtain one or more identifiers, and compare the identifiers against one or more programmable lookup tables. Based on this comparison, the bridge can determine the security status of the transaction, as well as selectively forward the transaction based on the security status.
Managing reuse information with multiple translation stages
Granted: July 3, 2018
Patent Number:
10013360
Address translation and caching is managed using a processor that includes at least one CPU configured to run a hypervisor at a first access level and at least one guest operating system at a second access level. The managing includes: at the second access level, translating from virtual addresses to intermediate physical; at the second access level, determining reuse information for ranges of virtual addresses based on estimated reuse of data stored within a virtual address space; at…
Managing memory access requests with prefetch for streams
Granted: July 3, 2018
Patent Number:
10013357
Managing memory access requests to a cache system including one or more cache levels that are configured to store cache lines that correspond to memory blocks in a main memory includes: storing stream information identifying recognized streams that were recognized based on previously received memory access requests, where one or more of the recognized streams comprise strided streams that each have an associated strided prefetch result corresponding to a stride that is larger than or…
Apparatus and method of generating lookups and making decisions for packet modifying and forwarding in a software-defined network engine
Granted: June 26, 2018
Patent Number:
10009273
Embodiments of the present invention relate to a Lookup and Decision Engine (LDE) for generating lookup keys for input tokens and modifying the input tokens based on contents of lookup results. The input tokens are parsed from network packet headers by a Parser, and the tokens are then modified by the LDE. The modified tokens guide how corresponding network packets will be modified or forwarded by other components in a software-defined networking (SDN) system. The design of the LDE is…
Method and apparatus for determining metric for selective caching
Granted: June 26, 2018
Patent Number:
10007614
System and method determining metric for selective caching, comprising determining a result of an access to a cache for at least one tracked attribute; determining a count value for the at least one tracked attribute in a translation look-aside buffer entry corresponding to the access to the cache in accordance with the determined result; comparing the count value for the at least one tracked attribute with a threshold associated with the at least one tracked attribute; assigning the…
Managing history information for branch prediction
Granted: June 26, 2018
Patent Number:
10007524
Branch history information characterizes results of branch instructions previously executed by a processor. A count is stored of a number of consecutive branch instructions previously executed by the processor whose results all indicate a not taken branch. In a first pipeline stage, a predicted branch result is provided based on at least a portion of the branch history information, and one or more of the branch history information, and the count, is updated based on the predicted branch…
Packet tracking in a verification environment
Granted: June 26, 2018
Patent Number:
10006963
A testbench, including a verification environment, tests a device under test (DUT). A packet tracking module, which is verification environment agnostic, is configured to track packets in the verification environment. The packet tracking module maintains an associative data structure of packet identifiers that are indexed by a unique value, a counter for identifying the packets in the verification environment, and a set of routines for tracking the packets in the verification environment…
System and method for configuring a plurality of registers with soft error detection and low wiring complexity
Granted: June 19, 2018
Patent Number:
10001999
A new approach is proposed which contemplates system and method for configuring a plurality of configurable registers in a programmable digital processing engine of a network device. Under the proposed approach, one or more slave configuration controllers (SCC) are utilized to configure a large number of configurable registers in a programmable engine, wherein each SCC is used to configure a plurality of configurable registers, which are organized in multiple configuration groups. The…
Verification of a multichip coherence protocol
Granted: June 19, 2018
Patent Number:
10002218
A system includes a formal verification engine running on a host and a protocol checking engine. The formal verification engine automatically generates and formally verifies a reference specification that includes a plurality of extended state tables for an integrated circuit (IC) design protocol of a chip at architectural level. The formal verification engine is further configured to automatically generate a plurality of self-contained services from the plurality of extended state…
Systems and methods for dynamic regression test generation using coverage-based clustering
Granted: June 19, 2018
Patent Number:
10002216
A new approach is proposed that contemplates systems and methods to support dynamic regression test generation for an IC design based upon coverage-based clustering of RTL modules in the design. First, coverage data for code coverage by a plurality of RTL modules in the IC design are collected and a plurality of clusters of related RTL modules of the IC design are generated based on statistical analysis of the collected coverage data and hierarchal information of the RTL modules. When…
Arbitrated access to resources among multiple devices
Granted: June 19, 2018
Patent Number:
10002099
An arbiter circuit manages and enforces arbitration and quality of service (QOS) among multiple devices accessing a resource, such as a memory. The arbiter circuit receives requests from a number of devices to use resources of a bridge connecting to a memory, and maintains a count of bridge resources available on a per-device and per-bus basis. The arbiter circuit operates to select a next one of the requests to grant a bridge resource based on the device originating the request, a count…
