Systems and methods for dynamic regression test generation using coverage-based clustering
Granted: June 19, 2018
Patent Number:
10002216
A new approach is proposed that contemplates systems and methods to support dynamic regression test generation for an IC design based upon coverage-based clustering of RTL modules in the design. First, coverage data for code coverage by a plurality of RTL modules in the IC design are collected and a plurality of clusters of related RTL modules of the IC design are generated based on statistical analysis of the collected coverage data and hierarchal information of the RTL modules. When…
Arbitrated access to resources among multiple devices
Granted: June 19, 2018
Patent Number:
10002099
An arbiter circuit manages and enforces arbitration and quality of service (QOS) among multiple devices accessing a resource, such as a memory. The arbiter circuit receives requests from a number of devices to use resources of a bridge connecting to a memory, and maintains a count of bridge resources available on a per-device and per-bus basis. The arbiter circuit operates to select a next one of the requests to grant a bridge resource based on the device originating the request, a count…
System and method for configuring a plurality of registers with soft error detection and low wiring complexity
Granted: June 19, 2018
Patent Number:
10001999
A new approach is proposed which contemplates system and method for configuring a plurality of configurable registers in a programmable digital processing engine of a network device. Under the proposed approach, one or more slave configuration controllers (SCC) are utilized to configure a large number of configurable registers in a programmable engine, wherein each SCC is used to configure a plurality of configurable registers, which are organized in multiple configuration groups. The…
Two modes of a configuration interface of a network ASIC
Granted: June 5, 2018
Patent Number:
9990324
Embodiments of the present invention are directed to a configuration interface of a network ASIC. The configuration interface allows for two modes of traversal of nodes. The nodes form one or more chains. Each chain is in a ring or a list topology. A master receives external access transactions. Once received by the master, an external access transaction traverses the chains to reach a target node. A target node either is an access to a memory space or is a module. A chain can include at…
Method and apparatus for providing a low latency transmission system using adaptive buffering estimation
Granted: May 29, 2018
Patent Number:
9985887
One aspect of the present invention discloses a network system capable of transmitting and processing audio video (“A/V”) data with enhanced quality of service (“QoS”). The network system includes a transmitter, a transmission channel, an adjustable decoder buffer, and a decoder. The transmitter contains an encoder able to encode A/V data in accordance with encoding bit rate recommendation from SQoS and packets loss notifications. The transmission channel, in one example,…
Method and an apparatus for memory address allignment
Granted: May 22, 2018
Patent Number:
9977737
A method and a system embodying the method for a memory address alignment, comprising configuring one or more naturally aligned buffer structure(s); providing a return address pointer in a buffer of one of the one or more naturally aligned buffer structure(s); determining a configuration of the one of the one or more naturally aligned buffer structure(s); applying a modulo arithmetic to the return address and at least one parameter of the determined configuration; and providing a stacked…
Multi-phase divider
Granted: May 8, 2018
Patent Number:
9966964
An example embodiment disclosed herein enables at least one frequency divider chain of a multiphase divider circuit to ensure proper phase relations after multiple frequency divisions. Another example embodiment enables a unique reset sequence to maximize a timing margin for reset signals of the at least one frequency divider chain and, thus, maximizes a bandwidth of the multiphase divider circuit.
Method of modifying packets to a generic format for enabling programmable modifications and an apparatus thereof
Granted: May 1, 2018
Patent Number:
9961167
Embodiments of the apparatus for modifying packet headers relate to a rewrite engine that represents each protocol header of packets in a generic format specific to that protocol to enable programmable modifications of packets, resulting in hardware and software flexibility in modifying packet headers. Software programs generic formats in a hardware table for various protocols. The rewrite engine is able to detect missing fields from a protocol header and is able to expand the protocol…
Methods and systems for direct memory access operations
Granted: April 24, 2018
Patent Number:
9952979
Systems and methods for a direct memory access (DMA) operation are provided. The method includes receiving a host memory address by a device coupled to a computing device; storing the host memory address at a device memory by a DMA engine; receiving a packet at the device for the computing device; instructing the DMA engine by a device processor to retrieve the host memory address from the device memory; retrieving the host memory address by the DMA engine without the device processor…
Barrel compactor system, method and device
Granted: April 24, 2018
Patent Number:
9954551
A packet processing system having a barrel compactor that extracts a desired data subset from an input dataset (e.g. an incoming packet). The barrel compactor is able to selectively shift one or more of the input data units of the input dataset based on individual shift values for those data units. Additionally, in some embodiments one or more of the data units are able to be logically combined to produce a desired logical output unit.
Method and system for reconfigurable parallel lookups using multiple shared memories
Granted: April 24, 2018
Patent Number:
9952800
Embodiments of the present invention relate to multiple parallel lookups using a pool of shared memories by proper configuration of interconnection networks. The number of shared memories reserved for each lookup is reconfigurable based on the memory capacity needed by that lookup. The shared memories are grouped into homogeneous tiles. Each lookup is allocated a set of tiles based on the memory capacity needed by that lookup. The tiles allocated for each lookup do not overlap with other…
Method and system for reconfigurable parallel lookups using multiple shared memories
Granted: April 24, 2018
Patent Number:
9952799
Embodiments of the present invention relate to multiple parallel lookups using a pool of shared memories by proper configuration of interconnection networks. The number of shared memories reserved for each lookup is reconfigurable based on the memory capacity needed by that lookup. The shared memories are grouped into homogeneous tiles. Each lookup is allocated a set of tiles based on the memory capacity needed by that lookup. The tiles allocated for each lookup do not overlap with other…
Apparatus and method for enabling flexible key in a network switch
Granted: April 17, 2018
Patent Number:
9948482
A network switch to support flexible lookup key generation comprises a control CPU configured to run a network switch control stack. The network switch control stacks is configured to manage and control operations of a switching logic circuitry, provide a flexible key having a plurality of possible fields that constitute part of a lookup key to a table, and enable a user to dynamically select at deployment or runtime a subset of the fields in the flexible key to form the lookup key and…
Methods and systems for processing read and write requests
Granted: April 17, 2018
Patent Number:
9946671
Methods and systems for processing an input/output (I/O) requests are provided. The method includes generating an I/O request by an initiator adapter of a computing device that interfaces with a target adapter; indicating by the initiator adapter that the I/O request is sequential in nature. When the I/O request is a sequential read request, the target adapter notifies a target controller to read-ahead data associated with other sequential read requests; and stores the read ahead data at…
Methods and systems for a multi-function adapter
Granted: April 3, 2018
Patent Number:
9936021
Systems and methods for storage operations are provided. As an example, a method includes configuring a non-volatile memory of a network device to be used as a storage device for storing data for an application; generating a logical storage object for the application for using storage space at the non-volatile memory of the network device to store data for the application, where the network device creates a unique identifier for the logical storage object; identifying the logical storage…
Method and system for transmitting information in a network
Granted: April 3, 2018
Patent Number:
9936003
Methods and systems for transmitting information are provided. A threshold message size is configured to determine when an application executed by a computing system can send a latency message identifying a memory location from where a device can procure a payload for transmission to a destination. The computing system sends a latency message to the device, where the latency message includes the memory location, a transfer size and an indicator indicating if the application wants a…
Methods and systems for accessing storage using a network interface card
Granted: April 3, 2018
Patent Number:
9934177
Methods and systems for efficiently processing input/output requests are provided. A network interface card (NIC) is coupled to a storage device via a peripheral link and accessible to a processor of a computing device executing instructions out of a memory device. The NIC is configured to receive a read/write request to read/write data; translate the read/write request to a storage device protocol used by the storage device coupled to the NIC; notify the storage device of the read/write…
Automatic data rate matching
Granted: April 3, 2018
Patent Number:
9933809
Pacing of a producer, operating in a producer clock domain, may be based on at least one heuristic of a credit wire that is used to return credits to the producer. The returned credits may indicate that a consumer, operating in a consumer clock domain, has consumed data produced by the producer. The at least one heuristic may be a rate at which the credits are returned to the producer. Pacing the producer based on the rate at which the credits are returned to the producer may reduce…
Distributed timer subsystem
Granted: March 27, 2018
Patent Number:
9928193
A silicon device configured to distribute a global timer value over a single serial bus to a plurality of processing elements that are disposed on the silicon device and that are coupled to the serial bus. Each of the processing elements comprises a slave timer. Upon receipt of the global timer value, the processing elements synchronize their respective slave timers with the global timer value. After the timers are synchronized, the global timer sends periodic increment signals to each…
Apparatus and method for on-chip crossbar design in a network switch using benes network
Granted: March 13, 2018
Patent Number:
9916274
An on-chip crossbar of a network switch comprising a central arbitration component configured to allocate packet data requests received from destination port groups to memory banks. The on-chip crossbar further comprises a Benes routing network comprising a forward network having a plurality of pipelined forward routing stages and a reverse network, wherein the Benes routing network retrieves the packet data from the memory banks coupled to input of the Benes routing network and route…
