METHODS AND APPARATUS FOR PACKAGE SUBSTRATES WITH STACKS OF GLASS LAYERS HAVING DIFFERENT COEFFICIENTS OF THERMAL EXPANSION
Granted: January 2, 2025
Application Number:
20250006609
Systems, apparatus, articles of manufacture, and methods for package substrates with stacks of glass layers having different coefficients of thermal expansion are disclosed. An example package substrate includes: a first glass layer including a first through glass via extending therethrough, the first glass layer having a first coefficient of thermal expansion (CTE); and a second glass layer including a second through glass via extending therethrough, the second glass layer having a…
PERFORMANCE OPTIMIZATION OF TRANSISTORS SHARING CHANNEL STRUCTURES OF VARYING WIDTH
Granted: January 2, 2025
Application Number:
20250006734
An integrated circuit (IC) device includes a stripe of material perpendicular to, and spanning between, semiconductor structures with multiple widths, and the stripe is between transistors with channel regions of differing widths in the semiconductor structures. The material stripes cover transition portions between different widths of the semiconductor structures. The semiconductor structures may be channel structures of different types, including groups of fins or nanoribbons. Channel…
CELL ROWS WITH MIXED HEIGHTS AND MIXED NANORIBBON WIDTHS
Granted: January 2, 2025
Application Number:
20250006721
Techniques are described for designing and forming cells comprising transistor devices for an integrated circuit. In an example, an integrated circuit structure includes a plurality of cells arranged in rows where some rows have different cell heights compared to other rows. Additionally, the various rows of cells may contain semiconductor nanoribbons having different widths between different rows. For example, any number of first rows of cells can each have a first height and any number…
THROUGH GLASS VIAS WITH COMPLIANT LAYER FOR INTEGRATED CIRCUIT DEVICE PACKAGES
Granted: January 2, 2025
Application Number:
20250006646
Integrated circuit (IC) die packages including a glass with conductive through-glass vias (TGVs). The TGVs are lined with a buffer comprising an inorganic material having a low elastic (Young's) modulus. The buffer may thereby accommodate internal stress between the glass and through via metallization formed over the buffer. The compliant inorganic material may be a metal or metal alloy, for example, different than that of the via metallization. The inorganic material may also be a metal…
MICROELECTRONIC ASSEMBLIES INCLUDING A PHOTOIMAGEABLE DIELECTRIC FOR HYBRID BONDING AND DIE ENCAPSULATION
Granted: January 2, 2025
Application Number:
20250006645
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer of a substrate including a first material having a cavity and a conductive pad at a bottom of the cavity; a first microelectronic component having a first surface and an opposing second surface, the first microelectronic component in the cavity and electrically coupled to the conductive pad at the bottom of the cavity; a second layer of…
METHODS OF FORMING WAFER LEVEL MULTI-DIE SYSTEM FABRIC INTERCONNECT STRUCTURES
Granted: January 2, 2025
Application Number:
20250006643
Microelectronic integrated circuit package structures include a package substrate with a first die over the package substrate, and a second die adjacent to the first die, such that first sides of the first die and the second die are on a thermal solution. A bridge structure is directly on a portion of each of second sides of the first and second dies, such that the second sides include integrated circuit contact structures. Bridge via structures couple the integrated circuit contact…
Routing and Passive Components in a Direct Bonding Layer
Granted: January 2, 2025
Application Number:
20250006630
Described herein are integrated circuit devices that include conductive structures formed by direct bonding of different components, e.g., direct bonding of two dies, or of a die to a wafer. The conductive structures are formed from a top metallization layer of each of the components. For example, elongated conductive structures at the top metallization layer may be patterned and bonded to form large interconnects for high-frequency and/or high-power signals. In another example, the…
METHODS AND APPARATUS FOR POWER DELIVERY THROUGH PACKAGE SUBSTRATES WITH STACKS OF GLASS LAYERS HAVING DIFFERENT COEFFICIENTS OF THERMAL EXPANSION
Granted: January 2, 2025
Application Number:
20250006612
Systems, apparatus, articles of manufacture, and methods for power delivery through package substrates with stacks of glass layers having different coefficients of thermal expansion are disclosed. An example substrate for an integrated circuit package includes: a first glass layer having a first coefficient of thermal expansion (CTE); a second glass layer having a second CTE, the second CTE different from the first CTE; a conductive material extending through a first hole in the first…
METHODS AND APPARATUS FOR POWER DELIVERY THROUGH PACKAGE SUBSTRATES WITH STACKS OF GLASS LAYERS HAVING DIFFERENT COEFFICIENTS OF THERMAL EXPANSION
Granted: January 2, 2025
Application Number:
20250006611
Systems, apparatus, articles of manufacture, and methods for power delivery through package substrates with stacks of glass layers having different coefficients of thermal expansion are disclosed. An example integrated circuit (IC) package includes: a package core including a first glass sheet and a second glass sheet distinct from the first glass sheet, the first glass sheet having a different coefficient of thermal expansion (CTE) from the second glass sheet; a first redistribution…
METHODS AND APPARATUS FOR POWER DELIVERY THROUGH PACKAGE SUBSTRATES WITH STACKS OF GLASS LAYERS HAVING DIFFERENT COEFFICIENTS OF THERMAL EXPANSION
Granted: January 2, 2025
Application Number:
20250006610
Systems, apparatus, articles of manufacture, and methods for power delivery through package substrates with stacks of glass layers having different coefficients of thermal expansion are disclosed. An example substrate for an integrated circuit package includes: a first glass layer having a first coefficient of thermal expansion (CTE); a second glass layer having a second CTE, the second CTE different from the first CTE; and a magnetic material lining a first wall of a first opening in…
TECHNOLOGIES FOR SUBSTRATE FEATURES FOR A PLUGGABLE OPTICAL CONNECTOR
Granted: January 2, 2025
Application Number:
20250004225
Technologies for substrate features for a pluggable optical connectors in an integrated circuit package are disclosed. In the illustrative embodiment, a substrate includes a cavity cut through a substrate of the integrated circuit package. Sidewalls of the cavity establish coarse lateral alignment features for an optical plug. The optical plug and optical socket include additional alignment features to more precisely align optical fibers in the optical plug to an optical interposer…
LOW-RESISTANCE VIA STRUCTURES
Granted: January 2, 2025
Application Number:
20250006592
Techniques to form low-resistance vias are discussed. In an example, semiconductor devices of a given row each include a semiconductor region extending in a first direction between corresponding source or drain regions, and a gate structure extending in a second direction over the semiconductor regions. Any semiconductor device may be separated from an adjacent semiconductor device along the second direction by a dielectric structure, through which a via passes. The via may include a…
GLASS CORES INCLUDING MULTIPLE LAYERS AND RELATED METHODS
Granted: January 2, 2025
Application Number:
20250006570
Glass cores including multiple layers and related methods are disclosed. An apparatus disclosed herein includes a printed circuit board and an integrated circuit package coupled to the printed circuit board, the integrated circuit package including a die and a glass core including a first layer having a first coefficient of thermal expansion and a second layer having a second coefficient of thermal expansion different than the first coefficient of thermal expansion.
REDUCED TUNGSTEN GALVANIC CORROSION IN WET CLEANING FOR ADVANCED SEMICONDUCTOR METALLIZATION FEATURES
Granted: January 2, 2025
Application Number:
20250006554
Devices, systems, and techniques are described herein related to reducing or eliminating galvanic corrosion of tungsten conductive features within tungsten-boron liners during wet clean thereof. The tungsten-boron liner is treated with a hydrogen/nitrogen plasma to modify a portion of the liner extending from the top surface to include tungsten, boron, nitrogen, and optionally oxygen. The modified portion of the liner reduces or eliminates galvanic corrosion during wet etch clean.
BACKLIGHT ADJUSTMENT TECHNOLOGIES
Granted: January 2, 2025
Application Number:
20250006139
A system that includes at least one processor that is to execute a software to: determine pixel value adjustments based on a limit on contrast loss and to reduce power consumption of a display connected to the display interface and provide the pixel value adjustments to the display interface to apply to pixels of a video frame.
COMPUTE OPTIMIZATION MECHANISM
Granted: January 2, 2025
Application Number:
20250005703
An apparatus to facilitate compute optimization is disclosed. The apparatus includes a mixed precision core including mixed-precision execution circuitry to execute one or more of the mixed-precision instructions to perform a mixed-precision dot-product operation comprising to perform a set of multiply and accumulate operations.
EXPLICIT INTEGRITY CHECK VALUE INITIALIZATION
Granted: January 2, 2025
Application Number:
20250005138
Techniques for explicit integrity check value initialization are described. In an embodiment, an apparatus includes an instruction decoder to decode a single instruction to set an integrity check value ICV corresponding to a destination location in a memory; and execution circuitry coupled to the instruction decoder, the execution circuitry to perform one or more operations corresponding to the single instruction, including storing data indicated by the single instruction into the…
INSTRUCTION TAGGING FOR INTRA-OBJECT MEMORY TAGGING
Granted: January 2, 2025
Application Number:
20250005137
Techniques for instruction tagging for intra-object memory tagging are described. In an embodiment, an apparatus includes an instruction decoder to decode a first instruction having an instruction tag value; and execution circuitry coupled to the instruction decoder, the execution circuitry to perform one or more operations corresponding to the first instruction, including generating a first data tag value based on the instruction tag value and a relative enumeration in a pointer to…
MULTI-TILE MEMORY MANAGEMENT
Granted: January 2, 2025
Application Number:
20250004981
Methods and apparatus relating to techniques for multi-tile memory management. In an example, a graphics processor includes an interposer, a first chiplet coupled with the interposer, the first chiplet including a graphics processing resource and an interconnect network coupled with the graphics processing resource, cache circuitry coupled with the graphics processing resource via the interconnect network, and a second chiplet coupled with the first chiplet via the interposer, the second…
ADAPTERS FOR HETEROGENOUS OPTICAL CONNECTORS
Granted: January 2, 2025
Application Number:
20250004227
Embodiments of optical adapters, and methods of forming and using the same, are disclosed herein. In one example, an optical adapter includes a first interface to mate with a first optical connector, a second interface to mate with a second optical connector, and a plurality of waveguides extending through the optical adapter from the first interface to the second interface. The first interface includes a first set of alignment features to align the optical adapter with the first optical…
