PEROVSKITE OXIDE FIELD EFFECT TRANSISTOR WITH HIGHLY DOPED SOURCE AND DRAIN
Granted: January 2, 2025
Application Number:
20250006791
Perovskite oxide field effect transistors comprise perovskite oxide materials for the channel, source, drain, and gate oxide regions. The source and drain regions are doped with a higher concentration of n-type or p-type dopants (depending on whether the transistor is an n-type or p-type transistor) than the dopant concentration in the channel region to minimize Schottky barrier height between the source and drain regions and the source and drain metal contact and contact resistance.
SELF-ALIGNED MEMORY CELL WITH REPLACEMENT METAL GATE VERTICAL ACCESS TRANSISTOR AND STACKED 3D CAPACITORS
Granted: January 2, 2025
Application Number:
20250008740
An integrated circuit device includes a stack of capacitors with a vertical first electrode coupled to a stack of individual second electrodes by an insulating storage material between first and second electrodes, and an access transistor coaxially aligned with, and coupled to, the vertical first electrode. The storage material may be a ferroelectric material. A gate dielectric of the access transistor may be around, and coaxial with, a channel region. The channel region may be…
HIGH-FREQUENCY INTERFACE CIRCUIT PROTECTION FROM ELECTROSTATIC DISCHARGE EVENTS
Granted: January 2, 2025
Application Number:
20250007278
An integrated circuit (IC) device comprises a conductive contact at a surface of the IC device. First and second circuitry are coupled with the conductive contact. First and second supply lines are coupled with and provide power to the first circuitry, the first supply line providing a first voltage, and the second supply line providing a second voltage. The second circuitry is further coupled with the second supply line and a third supply line. The third supply line is to provide a…
Adaptive Battery Usage Window to Extend Battery Longevity
Granted: January 2, 2025
Application Number:
20250007017
Methods and apparatus relating to an adaptive battery usage window to extend battery longevity are described. In an embodiment, a State Of Charge (SOC) for a rechargeable battery is controlled based on a plurality of limited charging modes that may selectively allow/prevent charging/discharging of the rechargeable battery to target level(s). Other embodiments are also disclosed and claimed.
TECHNOLOGIES FOR BARRIER LAYERS IN PEROVSKITE TRANSISTORS
Granted: January 2, 2025
Application Number:
20250006841
Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a transistor includes a gate of strontium ruthenate and a ferroelectric gate dielectric layer of barium titanate. In order to prevent migration of ruthenium from the strontium ruthenate to the barium titanate, a barrier layer is placed between the gate and the ferroelectric gate dielectric layer. The barrier layer may be a metal oxide, such as strontium…
NEGATIVE CAPACITANCE FIELD EFFECT TRANSISTOR (NCFET) DEVICES
Granted: January 2, 2025
Application Number:
20250006840
In one embodiment, a negative capacitance transistor device includes a perovskite semiconductor material layer with first and second perovskite conductors on opposite ends of the perovskite semiconductor material layer. The device further includes a dielectric material layer on the perovskite semiconductor material layer between the first and second perovskite conductors, a perovskite ferroelectric material layer on the dielectric material layer, and a third perovskite conductor on the…
P-TYPE PEROVSKITE FERROELECTRIC FIELD EFFECT TRANSISTOR (FEFET) DEVICES
Granted: January 2, 2025
Application Number:
20250006839
A transistor device may include a first perovskite gate material, a first perovskite ferroelectric material on the first gate material, a first p-type perovskite semiconductor material on the first ferroelectric material, a second perovskite ferroelectric material on the first semiconductor material, a second perovskite gate material on the second ferroelectric material, a third perovskite ferroelectric material on the second gate material, a second p-type perovskite semiconductor…
N-TYPE TRANSISTOR FABRICATION IN COMPLEMENTARY FET (CFET) DEVICES
Granted: January 2, 2025
Application Number:
20250006812
N-type gate-all-around (nanosheet, nanoribbon, nanowire) field-effect transistors (GAAFETs) vertically stacked on top of p-type GAAFETs in complementary FET (CFET) devices comprise non-crystalline silicon layers that form the n-type transistor source, drain, and channel regions. The non-crystalline silicon layers can be formed via deposition, which can provide for a simplified processing flow to form the middle dielectric layer between the n-type and p-type GAAFETs relative to processing…
TRANSISTOR WITH CHANNEL-SYMMETRIC GATE
Granted: January 2, 2025
Application Number:
20250006810
Transistor structures with gate material self-aligned to underlying channel material. A channel mask material employed for patterning channel material is retained during selective formation of a second mask material upon exposed surfaces of gate material. The channel mask material is then thinned to expose a sidewall of adjacent gate material. The exposed gate material sidewall is laterally recessed to expand an opening beyond an edge of underlying channel material. A third mask material…
HIGH CONDUCTIVITY TRANSISTOR CONTACTS COMPRISING GALLIUM ENRICHED LAYER
Granted: January 2, 2025
Application Number:
20250006806
In some implementations, an apparatus may include a substrate having silicon. In addition, the apparatus may include a first layer of a source or drain region of a p-type transistor, the first layer positioned above the substrate, the first layer having boron, silicon and germanium. The apparatus may include a second layer coupled to the source or drain region, the second layer having a metal contact for the source or drain region. Moreover, the apparatus may include a third layer…
REDUCED TUNGSTEN GALVANIC CORROSION IN WET CLEANING FOR ADVANCED SEMICONDUCTOR METALLIZATION FEATURES
Granted: January 2, 2025
Application Number:
20250006554
Devices, systems, and techniques are described herein related to reducing or eliminating galvanic corrosion of tungsten conductive features within tungsten-boron liners during wet clean thereof. The tungsten-boron liner is treated with a hydrogen/nitrogen plasma to modify a portion of the liner extending from the top surface to include tungsten, boron, nitrogen, and optionally oxygen. The modified portion of the liner reduces or eliminates galvanic corrosion during wet etch clean.
TRANSISTORS WITH ANTIMONY AND PHOSPHORUS DOPED EPITAXIAL SOURCE/DRAIN LAYERS
Granted: January 2, 2025
Application Number:
20250006790
In some implementations, a device may include a channel material. In addition, the device may include a contact metal. The device may include a first layer between the channel material and the contact metal, the first layer having antimony and silicon. Moreover, the device may include a second layer between the contact metal and the first layer, the second layer having phosphorus and silicon.
METHODS AND APPARATUS FOR POWER DELIVERY THROUGH PACKAGE SUBSTRATES WITH STACKS OF GLASS LAYERS HAVING DIFFERENT COEFFICIENTS OF THERMAL EXPANSION
Granted: January 2, 2025
Application Number:
20250006610
Systems, apparatus, articles of manufacture, and methods for power delivery through package substrates with stacks of glass layers having different coefficients of thermal expansion are disclosed. An example substrate for an integrated circuit package includes: a first glass layer having a first coefficient of thermal expansion (CTE); a second glass layer having a second CTE, the second CTE different from the first CTE; and a magnetic material lining a first wall of a first opening in…
METHODS AND APPARATUS FOR PACKAGE SUBSTRATES WITH STACKS OF GLASS LAYERS HAVING DIFFERENT COEFFICIENTS OF THERMAL EXPANSION
Granted: January 2, 2025
Application Number:
20250006609
Systems, apparatus, articles of manufacture, and methods for package substrates with stacks of glass layers having different coefficients of thermal expansion are disclosed. An example package substrate includes: a first glass layer including a first through glass via extending therethrough, the first glass layer having a first coefficient of thermal expansion (CTE); and a second glass layer including a second through glass via extending therethrough, the second glass layer having a…
LOW-RESISTANCE VIA STRUCTURES
Granted: January 2, 2025
Application Number:
20250006592
Techniques to form low-resistance vias are discussed. In an example, semiconductor devices of a given row each include a semiconductor region extending in a first direction between corresponding source or drain regions, and a gate structure extending in a second direction over the semiconductor regions. Any semiconductor device may be separated from an adjacent semiconductor device along the second direction by a dielectric structure, through which a via passes. The via may include a…
STANDARD-CELL CIRCUITS TO MITIGATE SCALING-RELATED PARASITICS
Granted: January 2, 2025
Application Number:
20250006591
An integrated circuit (IC) device may include standard cells with multiple parallel paths interconnecting transistors at a device level and over a transistor, in a higher layer of an interconnect structure. The parallel paths may include multiple power supply via contacts on a transistor source structure and multiple supply interconnect lines over the transistor and coupling the transistor to an associated power supply. The parallel paths may include multiple output via contacts on an…
MITIGATION OF THRESHOLD VOLTAGE SHIFT IN BACKSIDE POWER DELIVERY USING BACKSIDE PASSIVATION LAYER
Granted: January 2, 2025
Application Number:
20250006579
Devices, transistor structures, systems, and techniques are described herein related to providing a backside passivation layer on a transistor semiconductor material. The semiconductor material is between source and drain structures, and a gate structure is adjacent a channel region of the semiconductor material. The passivation layer is formed as a conformal insulative layer on a backside of the semiconductor material and is then treated using an ozone/UV cure to remove trap charges…
METHODS AND APPARATUS FOR STACKS OF GLASS LAYERS INCLUDING THIN FILM CAPACITORS
Granted: January 2, 2025
Application Number:
20250006571
Systems, apparatus, articles of manufacture, and methods for stacks of glass layers including thin film capacitors are disclosed. An example substrate includes a first glass layer, a dielectric layer on the first glass layer, a second glass layer, the first glass layer between the dielectric layer and the second glass layer, and a capacitor in the layer.
GLASS CORES INCLUDING MULTIPLE LAYERS AND RELATED METHODS
Granted: January 2, 2025
Application Number:
20250006570
Glass cores including multiple layers and related methods are disclosed. An apparatus disclosed herein includes a printed circuit board and an integrated circuit package coupled to the printed circuit board, the integrated circuit package including a die and a glass core including a first layer having a first coefficient of thermal expansion and a second layer having a second coefficient of thermal expansion different than the first coefficient of thermal expansion.
METHODS AND APPARATUS FOR PACKAGE SUBSTRATES WITH STACKS OF GLASS LAYERS HAVING DIFFERENT COEFFICIENTS OF THERMAL EXPANSION
Granted: January 2, 2025
Application Number:
20250006569
Systems, apparatus, articles of manufacture, and methods for package substrates with stacks of glass layers having different coefficients of thermal expansion are disclosed. An example substrate for an integrated circuit package includes: a first glass layer having a first coefficient of thermal expansion (CTE); and a second glass layer having a second CTE, the second CTE different from the first CTE.
