STACKED CMOS TRANSISTOR STRUCTURES WITH COMPLEMENTARY CHANNEL MATERIALS
Granted: January 2, 2025
Application Number:
20250006737
A material stack comprising a plurality of bi-layers, each bi-layer comprising two semiconductor material layers, is fabricated into a transistor structure including a first stack of channel materials that is coupled to an n-type source and drain and in a vertical stack with a second stack of channel materials that is coupled to a p-type source drain. Within the first stack of channel material layers a first of two semiconductor material layers may be replaced with a first gate stack…
Adaptive Battery Usage Window to Extend Battery Longevity
Granted: January 2, 2025
Application Number:
20250007017
Methods and apparatus relating to an adaptive battery usage window to extend battery longevity are described. In an embodiment, a State Of Charge (SOC) for a rechargeable battery is controlled based on a plurality of limited charging modes that may selectively allow/prevent charging/discharging of the rechargeable battery to target level(s). Other embodiments are also disclosed and claimed.
TECHNOLOGIES FOR BARRIER LAYERS IN PEROVSKITE TRANSISTORS
Granted: January 2, 2025
Application Number:
20250006841
Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a transistor includes a gate of strontium ruthenate and a ferroelectric gate dielectric layer of barium titanate. In order to prevent migration of ruthenium from the strontium ruthenate to the barium titanate, a barrier layer is placed between the gate and the ferroelectric gate dielectric layer. The barrier layer may be a metal oxide, such as strontium…
NEGATIVE CAPACITANCE FIELD EFFECT TRANSISTOR (NCFET) DEVICES
Granted: January 2, 2025
Application Number:
20250006840
In one embodiment, a negative capacitance transistor device includes a perovskite semiconductor material layer with first and second perovskite conductors on opposite ends of the perovskite semiconductor material layer. The device further includes a dielectric material layer on the perovskite semiconductor material layer between the first and second perovskite conductors, a perovskite ferroelectric material layer on the dielectric material layer, and a third perovskite conductor on the…
P-TYPE PEROVSKITE FERROELECTRIC FIELD EFFECT TRANSISTOR (FEFET) DEVICES
Granted: January 2, 2025
Application Number:
20250006839
A transistor device may include a first perovskite gate material, a first perovskite ferroelectric material on the first gate material, a first p-type perovskite semiconductor material on the first ferroelectric material, a second perovskite ferroelectric material on the first semiconductor material, a second perovskite gate material on the second ferroelectric material, a third perovskite ferroelectric material on the second gate material, a second p-type perovskite semiconductor…
N-TYPE TRANSISTOR FABRICATION IN COMPLEMENTARY FET (CFET) DEVICES
Granted: January 2, 2025
Application Number:
20250006812
N-type gate-all-around (nanosheet, nanoribbon, nanowire) field-effect transistors (GAAFETs) vertically stacked on top of p-type GAAFETs in complementary FET (CFET) devices comprise non-crystalline silicon layers that form the n-type transistor source, drain, and channel regions. The non-crystalline silicon layers can be formed via deposition, which can provide for a simplified processing flow to form the middle dielectric layer between the n-type and p-type GAAFETs relative to processing…
TRANSISTOR WITH CHANNEL-SYMMETRIC GATE
Granted: January 2, 2025
Application Number:
20250006810
Transistor structures with gate material self-aligned to underlying channel material. A channel mask material employed for patterning channel material is retained during selective formation of a second mask material upon exposed surfaces of gate material. The channel mask material is then thinned to expose a sidewall of adjacent gate material. The exposed gate material sidewall is laterally recessed to expand an opening beyond an edge of underlying channel material. A third mask material…
HIGH CONDUCTIVITY TRANSISTOR CONTACTS COMPRISING GALLIUM ENRICHED LAYER
Granted: January 2, 2025
Application Number:
20250006806
In some implementations, an apparatus may include a substrate having silicon. In addition, the apparatus may include a first layer of a source or drain region of a p-type transistor, the first layer positioned above the substrate, the first layer having boron, silicon and germanium. The apparatus may include a second layer coupled to the source or drain region, the second layer having a metal contact for the source or drain region. Moreover, the apparatus may include a third layer…
PEROVSKITE OXIDE FIELD EFFECT TRANSISTOR WITH HIGHLY DOPED SOURCE AND DRAIN
Granted: January 2, 2025
Application Number:
20250006791
Perovskite oxide field effect transistors comprise perovskite oxide materials for the channel, source, drain, and gate oxide regions. The source and drain regions are doped with a higher concentration of n-type or p-type dopants (depending on whether the transistor is an n-type or p-type transistor) than the dopant concentration in the channel region to minimize Schottky barrier height between the source and drain regions and the source and drain metal contact and contact resistance.
TRANSISTORS WITH ANTIMONY AND PHOSPHORUS DOPED EPITAXIAL SOURCE/DRAIN LAYERS
Granted: January 2, 2025
Application Number:
20250006790
In some implementations, a device may include a channel material. In addition, the device may include a contact metal. The device may include a first layer between the channel material and the contact metal, the first layer having antimony and silicon. Moreover, the device may include a second layer between the contact metal and the first layer, the second layer having phosphorus and silicon.
METHODS AND APPARATUS FOR PACKAGE SUBSTRATES WITH STACKS OF GLASS LAYERS INCLUDING INTERCONNECT BRIDGES
Granted: January 2, 2025
Application Number:
20250006613
Systems, apparatus, articles of manufacture, and methods for package substrates with stacks of glass layers including interconnect bridges are disclosed. An example substrate for an integrated circuit package includes: a first glass layer having a cavity defined therein; a second glass layer different from the first glass layer; and an interconnect bridge at least partially in the cavity. The interconnect bridge electrically couples a first semiconductor die to a second semiconductor…
PERFORMANCE OPTIMIZATION OF TRANSISTORS SHARING CHANNEL STRUCTURES OF VARYING WIDTH
Granted: January 2, 2025
Application Number:
20250006734
An integrated circuit (IC) device includes a stripe of material perpendicular to, and spanning between, semiconductor structures with multiple widths, and the stripe is between transistors with channel regions of differing widths in the semiconductor structures. The material stripes cover transition portions between different widths of the semiconductor structures. The semiconductor structures may be channel structures of different types, including groups of fins or nanoribbons. Channel…
CELL ROWS WITH MIXED HEIGHTS AND MIXED NANORIBBON WIDTHS
Granted: January 2, 2025
Application Number:
20250006721
Techniques are described for designing and forming cells comprising transistor devices for an integrated circuit. In an example, an integrated circuit structure includes a plurality of cells arranged in rows where some rows have different cell heights compared to other rows. Additionally, the various rows of cells may contain semiconductor nanoribbons having different widths between different rows. For example, any number of first rows of cells can each have a first height and any number…
FIDUCIALS WITH UNDERLYING DUMMY METALLIZATION FOR INTEGRATED CIRCUIT DEVICE ALIGNMENT
Granted: January 2, 2025
Application Number:
20250006652
An apparatus comprising a first integrated circuit device, the first integrated circuit device comprising a first layer with an area comprising metallization and metal-free slits; and a fiducial in a second layer above the first layer, the fiducial formed over the area comprising the metallization and metal-free slits.
THROUGH GLASS VIAS WITH COMPLIANT LAYER FOR INTEGRATED CIRCUIT DEVICE PACKAGES
Granted: January 2, 2025
Application Number:
20250006646
Integrated circuit (IC) die packages including a glass with conductive through-glass vias (TGVs). The TGVs are lined with a buffer comprising an inorganic material having a low elastic (Young's) modulus. The buffer may thereby accommodate internal stress between the glass and through via metallization formed over the buffer. The compliant inorganic material may be a metal or metal alloy, for example, different than that of the via metallization. The inorganic material may also be a metal…
MICROELECTRONIC ASSEMBLIES INCLUDING A PHOTOIMAGEABLE DIELECTRIC FOR HYBRID BONDING AND DIE ENCAPSULATION
Granted: January 2, 2025
Application Number:
20250006645
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer of a substrate including a first material having a cavity and a conductive pad at a bottom of the cavity; a first microelectronic component having a first surface and an opposing second surface, the first microelectronic component in the cavity and electrically coupled to the conductive pad at the bottom of the cavity; a second layer of…
METHODS OF FORMING WAFER LEVEL MULTI-DIE SYSTEM FABRIC INTERCONNECT STRUCTURES
Granted: January 2, 2025
Application Number:
20250006643
Microelectronic integrated circuit package structures include a package substrate with a first die over the package substrate, and a second die adjacent to the first die, such that first sides of the first die and the second die are on a thermal solution. A bridge structure is directly on a portion of each of second sides of the first and second dies, such that the second sides include integrated circuit contact structures. Bridge via structures couple the integrated circuit contact…
Routing and Passive Components in a Direct Bonding Layer
Granted: January 2, 2025
Application Number:
20250006630
Described herein are integrated circuit devices that include conductive structures formed by direct bonding of different components, e.g., direct bonding of two dies, or of a die to a wafer. The conductive structures are formed from a top metallization layer of each of the components. For example, elongated conductive structures at the top metallization layer may be patterned and bonded to form large interconnects for high-frequency and/or high-power signals. In another example, the…
FORMING POROUS DIELECTRIC STRUCTURES WITH SPATIALLY-CONTROLLED POROSITY
Granted: January 2, 2025
Application Number:
20250006623
Microelectronic integrated circuit package structures include one or more integrated circuit (IC) package metallization levels comprising metallization features. A dielectric material is adjacent to one or more of the metallization features, where the dielectric material comprises a matrix material and a surfactant. A plurality of substantially spherical pores are within the matrix material, where the substantially spherical pores are surrounded by an outer shell comprising the matrix…
HYBRID METALLIZATION SURFACES FOR INTEGRATED CIRCUIT PACKAGES
Granted: January 2, 2025
Application Number:
20250006616
IC die package with hybrid metallization surfaces. Routing metallization features have lower surface roughness for reduced high-frequency signal transmission losses while IC die attach metallization features have higher surface roughness for greater adhesion. Routing and die attach features may be formed within a same package metallization level, for example with a plating process. An insulator material may be formed over the surface of the metallization features, for example with a dry…
