Edge computing local breakout
Granted: March 18, 2025
Patent Number:
12255972
The present disclosure describes local breakout for edge computing systems, wherein the local breakout selectively routes the traffic from/to a user equipment between an edge compute node or some other service such as a core network, cloud computing service, or the like. Packets related to microservices that are offered by the edge compute node are routed to the edge compute node instead of routing those packets to the core network, and packets that are not related to the microservices…
Dynamic application programming interface (API) contract generation and conversion through microservice sidecars
Granted: March 18, 2025
Patent Number:
12254361
Embodiments described herein are generally directed to the use of sidecars to perform dynamic Application Programming Interface (API) contract generation and conversion. In an example, a first sidecar of a source microservice intercepts a first call to a first API exposed by a destination microservice. The first call makes use of a first API technology specified by a first contract and is originated by the source microservice. An API technology is selected from multiple API technologies.…
Apparatuses and methods to accelerate matrix multiplication
Granted: March 18, 2025
Patent Number:
12254061
Methods and apparatuses relating to performing vector multiplication are described. Hardware accelerators to perform vector multiplication are also described. In one embodiment, a combined fixed-point and floating-point vector multiplication circuit includes at least one switch to change the circuit between a first mode and a second mode, where in the first mode, each multiplier of a set of multipliers is to multiply mantissas from a same element position of a first floating-point vector…
PCIe deterministic link training using OOB communications and enumeration optimization during different power-up states
Granted: March 18, 2025
Patent Number:
12253966
A Peripheral Component Interface Express (PCIe) card includes a circuit board, a device mounted on the circuit board, and a PCIe processor mounted on the circuit board. The PCIe processor is communicatively coupled to the device and a host processor of a host system. The PCIe processor is configured to detect a power signal on an auxiliary (AUX) power rail of the PCIe card. A periodic detection of a state of the device is performed based on detecting the power signal on the AUX power…
System for address mapping and translation protection
Granted: March 18, 2025
Patent Number:
12253958
This disclosure is directed to a system for address mapping and translation protection. In one embodiment, processing circuitry may include a virtual machine manager (VMM) to control specific guest linear address (GLA) translations. Control may be implemented in a performance sensitive and secure manner, and may be capable of improving performance for critical linear address page walks over legacy operation by removing some or all of the cost of page walking extended page tables (EPTs)…
Decision architecture for autonomous systems
Granted: March 11, 2025
Patent Number:
12248852
Various systems and methods implement a decision architecture for autonomous systems. An autonomous system framework includes a safety ring configured to interface with safety features of an autonomous system; a security ring configured to provide authentication and verification services to transactions passed through the security ring; a privacy ring configured to ensure privacy of a user of the autonomous system; a trustworthiness ring configured to log and provide transparency of…
Vertical edge blocking (VEB) technique for increasing patterning process margin
Granted: March 11, 2025
Patent Number:
12249541
Embodiments disclosed herein include semiconductor devices and methods of forming such semiconductor devices. In an embodiment, a method of fabricating a semiconductor device comprises, forming a first grating of parallel first lines, forming a second grating of parallel second lines, wherein the second lines are substantially orthogonal to the first lines, and wherein the first lines and second lines define a plurality of first openings, disposing a conformal mask layer over the first…
Encoding additional states in a three-dimensional crosspoint memory architecture
Granted: March 11, 2025
Patent Number:
12249372
A state may be encoded into a memory cell comprising a phase change material (PM) region and a select device (SD) region by: applying a first current in the memory cell over a first time period, wherein the first current applied over the first time period causes the PM region of the memory cell to be placed into an amorphous state and the SD region of the memory cell to be placed into an amorphous state; and applying a second current in the memory cell over a second time period after the…
Dynamic power adjustment for OLED panels
Granted: March 11, 2025
Patent Number:
12249297
Methods and systems for dynamically adjusting the power consumption of an organic light-emitting diode (OLED) panel are disclosed. In embodiments, a histogram of a frame to be displayed is generated, and a weighted dimming curve is generated, with heavier weighting given to mid-tone intensity pixels. High and low intensity pixels are left only minimally adjusted. The curve is then capped and smoothed to prevent artifacts and to preserve image contrast. Each pixel in the frame is then…
Apparatus and method for seamless container migration for graphics processors and associated devices
Granted: March 11, 2025
Patent Number:
12249004
Apparatus and method for migrating a container including graphics processor state. One embodiment of an apparatus comprises: a first graphics processor coupled to a first system memory; execution circuitry of the graphics processor to execute graphics operations of processes grouped into a plurality of containers, the execution circuitry to be shared by the plurality of containers; and a first container migration engine to migrate a first container of the plurality of containers to a…
Technologies for liquid cooling interfaces
Granted: March 11, 2025
Patent Number:
12248344
Techniques for liquid cooling interfaces with rotatable connector assemblies are disclosed. In one embodiment, a collar contacts flanges on two components of a connector assembly, preventing them from separating. In another embodiment, a housing is positioned around a stem component. The stem component has a gap between a top part and a bottom part held apart by pillars, allowing water to flow to a tubing fitting connected to the housing. A retainer on top of the stem component holds the…
Scalable gate control in quantum circuit assemblies
Granted: March 11, 2025
Patent Number:
12248848
Quantum circuit assemblies that employ active pulse shaping in order to be able to control states of a plurality of qubits with signal pulses propagated over a shared signal propagation channel are disclosed. An example quantum circuit assembly includes a quantum circuit component that includes a first qubit, associated with a first frequency to control the state of the first qubit, and a second qubit, associated with a second frequency to control the state of the second qubit. A shared…
Methods and apparatus for task relocation based on memory access patterns
Granted: March 11, 2025
Patent Number:
12248808
Methods, apparatus, systems, and articles of manufacture are disclosed to relocate a compute thread, the apparatus comprising control circuitry to maintain a location of a plurality of domain access counters associated with a plurality of compute-memory domains for a first compute thread, and an execution monitor to set a first domain access counter of the plurality of domain access counters, the first domain access counter associated with a first compute-memory domain of the…
Virtualization of interprocessor interrupts
Granted: March 11, 2025
Patent Number:
12248800
Embodiments of apparatuses, methods, and systems for virtualization of interprocessor interrupts are disclosed. In an embodiment, an apparatus includes a plurality of processor cores; an interrupt controller register; and logic to, in response to a write from a virtual machine to the interrupt controller register, record an interprocessor interrupt in a first data structure configured by a virtual machine monitor and send a notification of the interprocessor interrupt to at least one of…
Instruction length decoding
Granted: March 11, 2025
Patent Number:
12248785
A processor includes a binary translator an a decoder. The binary translator includes logic to analyze a stream of atomic instructions, identify words by boundary bits in the atomic instructions, generate a mask to identify the words, and load the mask and the plurality of words into an instruction cache line. The words include atomic instructions. At least one word includes more than one atomic instruction. The decoder includes logic to apply the mask to identify a first word from the…
Techniques to repurpose static random access memory rows to store a look-up-table for processor-in-memory operations
Granted: March 11, 2025
Patent Number:
12248696
Example compute-in-memory (CIM) or processor-in-memory (PIM) techniques using repurposed or dedicated static random access memory (SRAM) rows of an SRAM sub-array to store look-up-table (LUT) entries for use in a multiply and accumulate (MAC) operation.
Side-channel exploit detection
Granted: March 11, 2025
Patent Number:
12248570
The present disclosure is directed to systems and methods for detecting side-channel exploit attacks such as Spectre and Meltdown. Performance monitoring circuitry includes first counter circuitry to monitor CPU cache misses and second counter circuitry to monitor DTLB load misses. Upon detecting an excessive number of cache misses and/or load misses, the performance monitoring circuitry transfers the first and second counter circuitry data to control circuitry. The control circuitry…
Apparatus and method for role-based register protection for TDX-IO
Granted: March 11, 2025
Patent Number:
12248561
Apparatus and method for role-based register protection. For example, one embodiment of an apparatus comprises: one or more processor cores to execute instructions and process data, the one or more processor cores to execute one or more security instructions to protect a virtual machine or trusted application from a virtual machine monitor (VMM) or operating system (OS); an interconnect fabric to couple the one or more processor cores to a device; and security hardware logic to determine…
Authenticator-integrated generative adversarial network (GAN) for secure deepfake generation
Granted: March 11, 2025
Patent Number:
12248556
An apparatus to facilitate an authenticator-integrated generative adversarial network (GAN) for secure deepfake generation is disclosed. The apparatus includes one or more processors to: generate, by a generative neural network, samples based on feedback received from a discriminator neural network and from an authenticator neural network, the generative neural network aiming to trick the discriminator neural network to identify the generated samples as real content samples; digest, by…
Techniques to reduce memory power consumption during a system idle state
Granted: March 11, 2025
Patent Number:
12248356
Examples include techniques to reduce memory power consumption during a system idle state. Cores of a single socket multi-core processor may be mapped to different virtual non-uniform memory architecture (NUMA) nodes and a dynamic random access memory (DRAM) may be partitioned into multiple segments that are capable of having self-refresh operations separately deactivated or activated. Different segments from among the multiple segments of DRAM may be mapped to the virtual NUMA nodes to…
