Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages
Granted: March 4, 2025
Patent Number:
12243812
Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having a lower insulating layer disposed thereon. The substrate has a perimeter. A metallization structure is disposed on the lower insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. First and…
Quantum dot devices with fins
Granted: March 4, 2025
Patent Number:
12245523
Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate and a quantum well stack disposed on the substrate. The quantum well stack may include a quantum well layer and a back gate, and the back gate may be disposed between the quantum well layer and the substrate.
Default PDSCH beam setting and PDCCH prioritization for multi panel reception
Granted: March 4, 2025
Patent Number:
12245252
Various embodiments herein are directed to set physical downlink shared channel (PDSCH) default beam behavior for single transmission-reception point (TRP), single downlink control information (DCI) multi-TRP and multi-DCI multi-TRP operation, as well as physical downlink control channel (PDCCH) prioritization based on quasi-colocation (QCL) Type-D for multi-panel reception and single panel reception.
Reinforcement learning (RL) and graph neural network (GNN)-based resource management for wireless access networks
Granted: March 4, 2025
Patent Number:
12245052
A computing node to implement an RL management entity in an NG wireless network includes a NIC and processing circuitry coupled to the NIC. The processing circuitry is configured to generate a plurality of network measurements for a corresponding plurality of network functions. The functions are configured as a plurality of ML models forming a multi-level hierarchy. Control signaling from an ML model of the plurality is decoded, the ML model being at a predetermined level (e.g., a lowest…
Determining adaptive quantization matrices using machine learning for video coding
Granted: March 4, 2025
Patent Number:
12244807
Techniques related to adaptive quantization matrix selection using machine learning for video coding are discussed. Such techniques include applying a machine learning model to generate an estimated quantization parameter for a frame and selecting a set of quantization matrices for encode of the frame from a number of sets of quantization matrices based on the estimated quantization parameter.
Methods and apparatus to perform dirty region reads and writes to reduce memory bandwidth usage
Granted: March 4, 2025
Patent Number:
12244798
An example apparatus includes image processing circuitry to determine an uncovered region of a background image in a current video frame relative to the background image in a previous video frame, the uncovered region obscured in the previous video frame by a first foreground region of the previous video frame, and the uncovered region uncovered in the current video frame based on movement of a second foreground region in the current video frame relative to the first foreground region of…
Intelligent data forwarding in edge networks
Granted: March 4, 2025
Patent Number:
12244507
Systems and techniques for intelligent data forwarding in edge networks are described herein. A request may be received from an edge user device for a service via a first endpoint. A time value may be calculated using a timestamp of the request. Motion characteristics may be determined for the edge user device using the time value. A response to the request may be transmitted to a second endpoint based on the motion characteristics.
Forksheet transistors with dielectric or conductive spine
Granted: March 4, 2025
Patent Number:
12243875
Embodiments disclosed herein include forksheet transistor devices having a dielectric or a conductive spine. For example, an integrated circuit structure includes a dielectric spine. A first transistor device includes a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine. A second transistor device includes a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine. An N-type gate structure…
Fan out packaging pop mechanical attach method
Granted: March 4, 2025
Patent Number:
12243856
Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a mold over and around a first die and a first via. The semiconductor package has a conductive pad of a first redistribution layer disposed on a top surface of the first die and/or a top surface of the mold. The semiconductor package includes a second die having a solder ball coupled to a die pad on a bottom surface of the second die, where the solder ball of…
Hybrid conductive vias for electronic substrates
Granted: March 4, 2025
Patent Number:
12243825
An electronic substrate may be fabricated to include a fine pitch dielectric layer having an upper surface, a coarse pitch dielectric layer on the upper surface of the fine pitch dielectric layer, and at least one hybrid conductive via extending through the fine pitch dielectric layer and the coarse pitch dielectric layer. The hybrid conductive via is fabricated such that a portion thereof that extends through the fine pitch dielectric layer is smaller than a portion extending through…
Electronic device
Granted: March 4, 2025
Patent Number:
D1065180
Nested architectures for enhanced heterogeneous integration
Granted: March 4, 2025
Patent Number:
12243806
Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first…
Microelectronic structures including bridges
Granted: March 4, 2025
Patent Number:
12243792
Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.
Methods and apparatus to profile page tables for memory management
Granted: March 4, 2025
Patent Number:
12242721
Disclosed Methods, Apparatus, and articles of manufacture to profile page tables for memory management are disclosed. An example apparatus includes a processor to execute computer readable instructions to: profile a first page at a first level of a page table as not part of a target group; and in response to profiling the first page as not part of the target group, label a data page at a second level that corresponds to the first page as not part of the target group, the second level…
Data initialization techniques
Granted: March 4, 2025
Patent Number:
12242414
Methods and apparatus relating to data initialization techniques. In an example, an apparatus comprises a processor to read one or more metadata codes which map to one or more cache lines in a cache memory and invoke a random number generator to generate random numerical data for the one or more cache lines in response to a determination that the one more metadata codes indicate that the cache lines are to contain random numerical data. Other embodiments are also disclosed and claimed.
Apparatus and methods for universal serial bus 4 (USB4) data bandwidth scaling
Granted: March 4, 2025
Patent Number:
12242412
A data scaling module for USB4 that embodies display driver (DD) and connection manager (CM) operations. Periodic and aperiodic transfer requests are monitored. The periodic BW activity on periodic peripherals, such as display panels (DPs) is monitored, and determinations as to reduced periodic activity on a DP are made. Responsive to receiving a high aperiodic bandwidth request, the original refresh rate for the DP is reduced. The newly freed USB4 BW is provided for the aperiodic task.…
Processors, methods, systems, and instructions to support live migration of protected containers
Granted: March 4, 2025
Patent Number:
12242391
A processor includes a decode unit to decode an instruction that is to indicate a page of a protected container memory, and a storage location outside of the protected container memory. An execution unit, in response to the instruction, is to ensure that there are no writable references to the page of the protected container memory while it has a write protected state. The execution unit is to encrypt a copy of the page of the protected container memory. The execution unit is to store…
Power supply optimization based on interface card power enable signaling
Granted: March 4, 2025
Patent Number:
12242319
An interface card includes a circuit board, a device mounted on the circuit board, and a PMIC mounted on the circuit board. The PMIC includes a PMIC processor communicatively coupled to a host processor of a host system. The PMIC processor is configured to receive an input voltage signal from a power supply that is external to the interface card. The PMIC processor generates at least one output voltage signal based on the input voltage signal. The at least one output voltage signal is…
Thermal management in horizontally or vertically stacked dies
Granted: March 4, 2025
Patent Number:
12242315
A thermal management scheme, for a multichip module, that is aware of various dies in a stack (horizontal and/or vertical) and heat generated from them, local hot spots in a victim die, and hot spots in aggressor die(s). Each victim die receives telemetry information from thermal sensors located in aggressor dies as well as local thermal sensors in the victim die. The telemetry information is used to enable a virtual sensing scheme where temperature for a target die (e.g., a victim die)…
Integrating voltage regulators and passive circuit elements with top side power planes in stacked die architectures
Granted: March 4, 2025
Patent Number:
12242290
In one embodiment, an apparatus includes a first die with voltage regulator circuitry and a second die with logic circuitry. The apparatus further includes an inductor, a capacitor, and a conformal power delivery structure on the top side of the apparatus, where the voltage regulator circuitry is connected to the logic circuitry through the inductor, the capacitor, and the conformal power delivery structure. The conformal power delivery structure includes a first electrically conductive…
