Self-assembled guided hole and via patterning over grating
Granted: February 18, 2025
Patent Number:
12230536
Described herein are IC devices include vias deposited in a regular array, e.g., a hexagonal array, and processes for depositing vias in a regular array. The process includes depositing a guiding pattern over a metal grating, depositing a diblock copolymer over the guiding pattern, and causing the diblock copolymer to self-assemble such one polymer forms an array of cylinders over metal portions of the metal grating. The polymer layer can be converted into a hard mask layer, with one…
Integrated circuit structures having partitioned source or drain contact structures
Granted: February 18, 2025
Patent Number:
12230717
Integrated circuit structures having partitioned source or drain contact structures, and methods of fabricating integrated circuit structures having partitioned source or drain contact structures, are described. For example, an integrated circuit structure includes a fin. A gate stack is over the fin. A first epitaxial source or drain structure is at a first end of the fin. A second epitaxial source or drain structure is at a second end of the fin. A conductive contact structure is…
Self-aligned gate endcap (SAGE) architectures with vertical sidewalls
Granted: February 18, 2025
Patent Number:
12230714
Self-aligned gate endcap (SAGE) architectures with vertical sidewalls, and methods of fabricating self-aligned gate endcap (SAGE) architectures with vertical sidewalls, are described. In an example, an integrated circuit structure includes a semiconductor fin having sidewalls along a length of the semiconductor fin, each sidewall tapering outwardly from a top of the semiconductor fin toward a bottom of the semiconductor fin. A gate endcap isolation structure is spaced apart from the…
Gate-all-around integrated circuit structures having depopulated channel structures using selective bottom-up approach
Granted: February 18, 2025
Patent Number:
12230635
Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a selective bottom-up approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxide nanowires. A first gate stack is over…
Double-sided substrate with cavities for direct die-to-die interconnect
Granted: February 18, 2025
Patent Number:
12230610
Embodiments include a package substrate and semiconductor packages. A package substrate includes a first cavity in a top surface, first conductive pads on a first surface of the first cavity, a second cavity in a bottom surface, second conductive pads on a second surface of the second cavity, where the first surface is above the second surface, and a third cavity in the first and second cavities, where the third cavity vertically extends from the top surface to the bottom surface. The…
Embedded die on interposer packages
Granted: February 18, 2025
Patent Number:
12230582
Integrated circuit (IC) packages having a through-via interposer with an embedded die, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, an IC package may include a through-via interposer with an embedded die, the through-via connections having front to back conductivity. In some embodiments, a die may be disposed on the back side of an IC package having a through-via interposer with an embedded die and may be electrically…
Local density control for metal capacitance reduction
Granted: February 18, 2025
Patent Number:
12230577
An integrated circuit structure includes a plurality of interconnect lines and a plurality of dummy lines that are co-planar with the plurality of interconnect lines, where a ratio of line length to end-to-end spacing of the dummy lines varies inversely with a density of the interconnect lines within each of a plurality of regions. The regions are of approximately equal area within a rectangular grid array.
Apparatus and method to increase effective capacitance with layout staples
Granted: February 18, 2025
Patent Number:
12230569
A scheme intelligently balances existing TM0 resources to simultaneously boost both AC and DC power delivery topologies without incurring a penalty on either area or IR drop. TM0 tracks are either regular or staples. Regular tracks are continuous across the width of an active silicon. Staples are located right under the respective TM1 (Top Metal 1) tracks. TM1 is above TM0 in the hierarchy of metal layers. The staples aid in increasing the total TV0 (Top Via 0 that connects TM0 to TM1)…
Package substrate z-disaggregation with liquid metal interconnects
Granted: February 18, 2025
Patent Number:
12230564
A z-disaggregated integrated circuit package substrate assembly comprises a first substrate component (a coreless patch), a second substrate component (a core patch), and a third substrate component (an interposer). The coreless patch comprises thinner dielectric layers and higher density routing and can comprise an embedded bridge to allow for communication between integrated circuit dies attached to the coreless patch. The core layer acts as a middle layer interconnect between the…
Method to enable 30 microns pitch EMIB or below
Granted: February 18, 2025
Patent Number:
12230563
A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming…
Substrate embedded magnetic core inductors and method of making
Granted: February 18, 2025
Patent Number:
12230430
Described are microelectronic devices including an embedded microelectronic package for use as an integrated voltage regulator with a microelectronic system. The microelectronic package can include a substrate and a magnetic foil. The substrate can define at least one layer having one or more of electrically conductive elements separated by a dielectric material. The magnetic foil can have ferromagnetic alloy ribbons and can be embedded within the substrate adjacent to the one or more of…
Injury severity estimation by using in-vehicle perception
Granted: February 18, 2025
Patent Number:
12230402
A monitoring system may include a memory having computer-readable instructions stored thereon and a processor operatively coupled to the memory. The processor may read and execute the computer-readable instructions to perform or control performance of operations. The operations may include receive, prior to a collision involving a vehicle, sensor data representative of a feature of an internal environment and determine the collision has occurred. The operations may include automatically…
Cross-point memory read technique to mitigate drift errors
Granted: February 18, 2025
Patent Number:
12230346
A read technique for both SLC (single level cell) and MLC (multi-level cell) cross-point memory can mitigate drift-related errors with minimal or no drift tracking. In one example, a read at a higher magnitude voltage is applied first, which causes the drift for cells in a lower threshold voltage state to be reset. In one example, the read at the first voltage can be a full float read to minimize disturb. A second read can then be performed at a lower voltage without the need to adjust…
Apparatus and method for approximate trilinear interpolation for scene reconstruction
Granted: February 11, 2025
Patent Number:
12223615
A method comprising: dividing a 3D space into a voxel grid comprising a plurality of voxels; associating a plurality of distance values with the plurality of voxels, each distance value based on a distance to a boundary of an object; selecting an approximate interpolation mode for stepping a ray through a first one or more voxels of the 3D space responsive to the first one or more voxels having distance values greater than a threshold; and detecting the ray reaching a second one or more…
Forming an oxide volume within a fin
Granted: February 11, 2025
Patent Number:
12224202
Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes to form volumes of oxide within a fin, such as a Si fin. In embodiments, this may be accomplished by applying a catalytic oxidant material on a side of a fin and then annealing to form a volume of oxide. In embodiments, this may be accomplished by using a plasma implant technique or a beam-line implant technique to introduce oxygen ions into an area of the fin and then annealing to form a…
Angled inductor with small form factor
Granted: February 11, 2025
Patent Number:
12224103
An electronic substrate may be fabricated having a dielectric material, metal pads embedded in the dielectric material with co-planar surfaces spaced less than one tenth millimeter from each other, and a metal trace embedded in the dielectric material and attached between the metal pads, wherein a surface of the metal trace is non-co-planar with the co-planar surfaces of the metal pads at a height of less than one millimeter, and wherein sides of the metal trace are angled relative to…
Staggered active bitline sensing
Granted: February 11, 2025
Patent Number:
12224015
Systems, apparatuses and methods may provide for technology that applies a first set of control signals to even bitlines in NAND memory and senses voltage levels of the even bitlines during an even sensing time period. The technology may also apply a second set of control signals to odd bitlines in the NAND memory, and sense voltage levels of the odd bitlines during an odd sensing time period, wherein the second set of control signals are applied after expiration of a stagger time period…
Methods and apparatus for acoustic noise mitigation of electronic noise using adaptive sensing and control
Granted: February 11, 2025
Patent Number:
12223937
Methods, apparatus, systems and articles of manufacture for acoustic system noise mitigation are disclosed. An example apparatus includes a sound sensor and one or more electronic components. The apparatus also includes a background noise analyzer to obtain sensor data indicative of background noise in an environment of the apparatus from the sound sensor. The apparatus also includes a system noise analyzer to select a first system noise profile indicative of acoustic noise associated…
Methods and arrangements for sensors
Granted: February 11, 2025
Patent Number:
12223822
Example methods and arrangements for sensors are disclosed herein. At least one storage device or storage disk includes instructions that, when executed, cause at least one processor of a mobile electronic device to at least access notification data indicative of an event at a security perimeter of a building, the notification data corresponding to a change in a status of one or more sensors at the security perimeter; present the notification data to a user of the mobile electronic…
Variable width interleaved coding for graphics processing
Granted: February 11, 2025
Patent Number:
12223682
Variable width interleaved coding for graphics processing is described. An example of an apparatus includes one or more processors including a graphic processor; and memory for storage of data including data for graphics processing, wherein the graphics processor includes an encoder pipeline to provide variable width interleaved coding and a decoder pipeline to decode the variable width interleaved coding, and wherein the encoder pipeline is to receive a plurality of bitstreams from…
