Sensor for measuring liquid contaminants in a semiconductor wafer fabrication process
Granted: April 13, 2010
Patent Number:
7696538
Liquid detection sensors are attached to both sides of a robotic arm end effector of a semiconductor wafer process system. The sensor mechanism or probe is situated on the front side and backside of the end effector, designed with electrical lines that are traced onto a polyester base material. The electrical lines are positioned in a serpentine formation. The high conductance of the sulfuric acid in the copper sulfate solution acts as the conductor between the traced lines. When the…
Methods for producing low-stress carbon-doped oxide films with improved integration properties
Granted: April 13, 2010
Patent Number:
7695765
Methods of preparing a carbon doped oxide (CDO) layer with a low dielectric constant (<3.2) and low residual stress without sacrificing important integration properties such as refractive index and etch rate are provided. The methods involve, for instance, providing a substrate to a deposition chamber and exposing it to TMSA, followed by igniting and maintaining a plasma in a deposition chamber using radio frequency power having high and low frequency components or one frequency…
Small-volume electroless plating cell
Granted: April 6, 2010
Patent Number:
7690324
During fluid treatment of a substrate surface, a carrier/wafer assembly containing a substrate wafer closes the top of a microcell container. The carrier/wafer assembly and the container walls define a thin enclosed treatment volume that is filled with treating fluid, such as electroless plating solution. The thin fluid-treatment volume typically has a volume in a range of about from 100 ml to 500 ml. Preferably a container is heated and the treating fluid is pre-heated before being…
Deposition of tungsten nitride
Granted: April 6, 2010
Patent Number:
7691749
Methods for depositing a tungsten nitride layer are described. The methods form a tungsten nitride layer using a carefully controlled deposition technique such as pulsed nucleation layer (PNL). Initially, a tungsten layer is formed on a substrate surface. The tungsten layer is then exposed to a nitriding agent to form a tungsten nitride layer. Methods of forming relatively thick layers of involve repeated cycles of contact with reducing agent, tungsten precursor and nitriding agent. In…
Methods and apparatus for controlled-angle wafer positioning
Granted: March 30, 2010
Patent Number:
7686927
The orientation of a wafer with respect to the surface of an electrolyte is controlled during an electroplating process. The wafer is delivered to an electrolyte bath along a trajectory normal to the surface of the electrolyte. Along this trajectory, the wafer is angled before entry into the electrolyte for angled immersion. A wafer can be plated in an angled orientation or not, depending on what is optimal for a given situation. Also, in some designs, the wafer's orientation can be…
Pad-assisted electropolishing
Granted: March 30, 2010
Patent Number:
7686935
Pad-assisted electropolishing of the substrate is conducted by performing anodic dissolution of metal at a first portion of the substrate and simultaneously mechanically buffing a second portion of the substrate with a buffing pad. Anodic dissolution includes forming a thin liquid layer of electropolishing liquid between the anodic substrate and a cathodic electropolishing head. The location of electrical contacts between the substrate and power supply allow peripheral edge regions of…
Rotationally asymmetric variable electrode correction
Granted: March 23, 2010
Patent Number:
7682498
A work piece is electroplated or electroplanarized using an azimuthally asymmetric electrode. The azimuthally asymmetric electrode is rotated with respect to the work piece (i.e., either or both of the work piece and the electrode may be rotating). The azimuthal asymmetry provides a time-of-exposure correction to the current distribution reaching the work piece. In some embodiments, the total current is distributed among a plurality of electrodes in a reaction cell in order to tailor the…
Multistep method of depositing metal seed layers
Granted: March 23, 2010
Patent Number:
7682966
Metal seed layers are deposited on a semiconductor substrate having recessed features by a method that involves at least three operations. In this method, a first layer of metal is deposited onto the substrate to cover at least the bottom portions of the recessed features. The first layer of metal is subsequently redistributed to improve sidewall coverage of the recessed features. Next, a second layer of metal is deposited on at least the field region of the substrate and on the bottom…
Method of forming low-temperature conformal dielectric films
Granted: March 16, 2010
Patent Number:
7678709
A deposition method modulates the reaction rate and thickness of highly conformal dielectric films deposited by forming a saturated catalytic layer on the surface and then exposing the surface to silicon-containing precursor gas and a reaction modulator, which may accelerate or quench the reaction. The modulator may be added before, after, or during exposure of the silicon-containing precursor gas. The film thickness after one cycle of deposition may be increased up to 20 times or…
Methods for fabricating semiconductor structures with backside stress layers
Granted: March 2, 2010
Patent Number:
7670931
Methods for fabricating semiconductor structures with backside stress layers are provided. In one exemplary embodiment, the method comprises the steps of providing a semiconductor device formed on and within a front surface of a semiconductor substrate. The semiconductor device comprises a channel region. A plurality of dielectric layers is formed overlying the semiconductor device. The plurality of dielectric layers comprises conductive connections that are in electrical communication…
Selective resputtering of metal seed layers
Granted: February 9, 2010
Patent Number:
7659197
Metal seed layers are deposited on a semiconductor substrate having recessed features by a method that involves depositing a first portion of seed layer material, subsequently selectively resputtering the deposited seed layer material in the presence of exposed diffusion barrier material, and, depositing a second portion of the seed layer material. Resputtering operation improves seed layer coverage on the recessed feature sidewalls by redistributing seed layer material within the…
Methods for improving uniformity and resistivity of thin tungsten films
Granted: February 2, 2010
Patent Number:
7655567
The methods described herein relate to deposition of low resistivity, highly conformal tungsten nucleation layers. These layers serve as a seed layers for the deposition of a tungsten bulk layer. The methods are particularly useful for tungsten plug fill in which tungsten is deposited in high aspect ratio features. The methods involve depositing a nucleation layer by a combined PNL and CVD process. The substrate is first exposed to one or more cycles of sequential pulses of a reducing…
System and method for electrochemical mechanical polishing
Granted: January 19, 2010
Patent Number:
7648622
A method and apparatus for electropolishing a conductive surface of a semiconductor wafer. The apparatus includes a polisher having at least one first electrode and at least one second electrode separated from one another by an isolation region. A moving mechanism rotates the wafer while the conductive surface of the wafer is moved linearly and parallel to a first direction, which varies an exposure of the relative surface areas of the conductive surface to the at least one first…
Interfacial layers for electromigration resistance improvement in damascene interconnects
Granted: January 19, 2010
Patent Number:
7648899
Protective caps residing at an interface between metal lines and dielectric diffusion barrier (or etch stop) layers are used to improve electromigration performance of interconnects. Protective caps are formed by depositing a source layer of dopant-generating material (e.g., material generating B, Al, Ti, etc.) over an exposed copper line, converting the upper portion of the source layer to a passivated layer (e.g., nitride or oxide) while allowing an unmodified portion of a…
Deposition of thin continuous PVD seed layers having improved adhesion to the barrier layer
Granted: January 12, 2010
Patent Number:
7645696
Methods of depositing thin seed layers that improve continuity of the seed layer as well as adhesion to the barrier layer are provided. According to various embodiments, the methods involve performing an etchback operation in the seed deposition chamber prior to depositing the seed layer. The etch step removes barrier layer overhang and/or oxide that has formed on the barrier layer. It some embodiments, a small deposition flux of seed atoms accompanies the sputter etch flux of argon…
Methods of forming moisture barrier for low k film integration with anti-reflective layers
Granted: January 5, 2010
Patent Number:
7642202
A nitrogen-free anti-reflective layer for use in semiconductor photolithography is fabricated in a chemical vapor deposition process, optionally plasma-enhanced, using a gaseous mixture of carbon, silicon, and oxygen sources. By varying the process parameters, a substantially hermetic layer with acceptable values of the refractive index n and extinction coefficient k can be obtained. The nitrogen-free moisture barrier anti-reflective layer produced by this technique improves plasma etch…
CMP apparatuses with polishing assemblies that provide for the passive removal of slurry
Granted: December 15, 2009
Patent Number:
7632170
Chemical mechanical planarization apparatuses with polishing assemblies that provide for the passive removal of slurry are provided. In accordance with an embodiment, a work piece polishing assembly comprises a polishing pad comprising a polishing surface and an exhaust aperture that extends through the polishing pad from the polishing surface and is configured to receive a slurry from the polishing surface. An underlying member is disposed underlying the polishing pad and comprises a…
VLSI fabrication processes for introducing pores into dielectric materials
Granted: December 8, 2009
Patent Number:
7629224
Porous dielectric layers are produced by introducing pores in pre-formed composite dielectric layers. The pores may be produced after the barrier material, the metal or other conductive material is deposited to form a metallization layer. In this manner, the conductive material is provided with a relatively smooth continuous surface on which to deposit.
CVD flowable gap fill
Granted: December 8, 2009
Patent Number:
7629227
Methods of lining and/or filling gaps on a substrate by creating flowable silicon oxide-containing films are provided. The methods involve introducing vapor-phase silicon-containing precursor and oxidant reactants into a reaction chamber containing the substrate under conditions such that a condensed flowable film is formed on the substrate. The flowable film at least partially fills gaps on the substrates and is then converted into a silicon oxide film. In certain embodiments, the…
Method of selective coverage of high aspect ratio structures with a conformal film
Granted: December 1, 2009
Patent Number:
7625820
Methods for forming thin dielectric films by selectively depositing a conformal film of dielectric material on a high aspect ratio structure have uses in semiconductor processing and other applications. A method for forming a dielectric film involves providing in a deposition reaction chamber a substrate having a gap on the surface. The gap has a top opening and a surface area comprising a bottom and sidewalls running from the top to the bottom. A conformal silicon oxide-based dielectric…
