Selectively accelerated plating of metal features
Granted: July 14, 2009
Patent Number:
7560016
To make a metal feature, a non-plateable layer is applied to a workpiece surface and then patterned to form a first plating region and a first non-plating region. Then, metal is deposited on the workpiece to form a raised field region in said first plating region and a recessed region in said first non-plating region. Then, an accelerator film is applied globally on the workpiece. A portion of the accelerator film is selectively removed from the field region, and another portion of the…
Electrostatic chuck assembly with capacitive sense feature, and related operating method
Granted: July 7, 2009
Patent Number:
7558045
A semiconductor workpiece processing system for treating a workpiece, such as a semiconductor wafer, is provided. A related operating control method is also provided. The system includes an electrostatic chuck configured to receive a workpiece, and a clamping voltage power supply coupled to the electrostatic chuck. The electrostatic chuck has a clamping electrode assembly, and the clamping voltage power supply is coupled to the clamping electrode assembly. The clamping voltage power…
Electrode and pad assembly for processing conductive layers
Granted: June 23, 2009
Patent Number:
7550070
An electrode assembly includes a distribution plate having a plurality of grooves that communicate with openings in an overlying polishing pad layer. The grooves include end openings that allow for draining of process solution, both during processing and subsequent cleaning/rinsing of the pad. Drainage occurs continually during processing, cleaning and rinsing, and so is constricted through the end openings relative to the grooves, to prevent wastage. The end openings are sufficiently…
Adhesion of tungsten nitride films to a silicon surface
Granted: June 23, 2009
Patent Number:
7550851
A process is described that forms a low resistivity connection between a tungsten layer and a silicon surface with high adherence of the tungsten to the silicon. The silicon surface is plasma-cleaned to remove native oxide. A very thin layer (one or more monolayers) of Si-NH2 is formed on the silicon surface, serving as an adhesion layer. A WNx layer is formed over the Si-NH2 layer, using an atomic layer deposition (ALD) process, to serve as a barrier layer. A thick tungsten layer is…
Chemical mechanical polishing assembly with altered polishing pad topographical components
Granted: June 9, 2009
Patent Number:
7544115
A chemical-mechanical polishing apparatus is provided that creates a uniform kinematical pattern on the surface of a wafer being polished. The apparatus may have a polishing pad comprising a polishing pad surface having a center point that lies within an axis of motion for the polishing pad and a plurality of grooves entrenched in the polishing pad surface and defining a pattern of shapes. The pattern has an axis of symmetry that is offset from the polishing pad surface center point. The…
Treatment of low k films with a silylating agent for damage repair
Granted: June 2, 2009
Patent Number:
7541200
The present invention provides methods of repairing damage to low-k dielectric film that is incurred by commonly used processes in IC fabrication. The methods may be integrated into an IC fabrication process flow at various stages. According to various embodiments, the methods of involve performing an IC fabrication process on a wafer on which a low-k film is deposited, and subsequently treating the film with a silylating agent to repair the damage done to the film during the process.…
Method and apparatus for uniform electropolishing of damascene IC structures by selective agitation
Granted: May 12, 2009
Patent Number:
7531079
The present invention pertains to apparatus and methods for planarization of metal surfaces having both recessed and raised features, over a large range of feature sizes. The invention accomplishes this by increasing the fluid agitation in raised regions with respect to recessed regions. That is, the agitation of the electropolishing bath fluid is agitated or exchanged as a function of elevation on the metal film profile. The higher the elevation, the greater the movement or exchange…
Fabrication of semiconductor interconnect structure
Granted: May 12, 2009
Patent Number:
7531463
An etching process for selectively etching exposed metal surfaces of a substrate and forming a conductive capping layer over the metal surfaces is described. In some embodiments, the etching process involves oxidation of the exposed metal to form a metal oxide that is subsequently removed from the surface of the substrate. The exposed metal may be oxidized by using solutions containing oxidizing agents such as peroxides or by using oxidizing gases such as those containing oxygen or…
Flowable film dielectric gap fill process
Granted: April 28, 2009
Patent Number:
7524735
Methods of this invention relate to filling gaps on substrates with a solid dielectric material by forming a flowable film in the gap. The flowable film provides consistent, void-free gap fill. The film is then converted to a solid dielectric material. In this manner gaps on the substrate are filled with a solid dielectric material. According to various embodiments, the methods involve reacting a dielectric precursor with an oxidant to form the dielectric material. In certain…
Plating method and apparatus for controlling deposition on predetermined portions of a workpiece
Granted: April 14, 2009
Patent Number:
7517444
The present invention relates to methods and apparatus for plating a conductive material on a workpiece surface in a highly desirable manner. Using a workpiece-surface-influencing device, such as a mask or sweeper, that preferentially contacts the top surface of the workpiece, relative movement between the workpiece and the workpiece-surface-influencing device is established so that an additive in the electrolyte solution disposed on the workpiece and which is adsorbed onto the top…
Pulsed bias having high pulse frequency for filling gaps with dielectric material
Granted: April 7, 2009
Patent Number:
7514375
During bottom filling of high aspect ratio gaps and trenches in an integrated circuit substrate using HDP-CVD, a pulsed HF bias is applied to the substrate. In some embodiments, pulsed HF bias is applied to the substrate during etching operations. The pulsed bias typically has a pulse frequency in a range of about from 500 Hz to 20 kHz and a duty cycle in a range of about from 0.1 to 0.95.
Apparatus and methods for deposition and/or etch selectivity
Granted: March 31, 2009
Patent Number:
7510634
Disclosed are apparatus and method embodiments for achieving etch and/or deposition selectivity in vias and trenches of a semiconductor wafer. That is, deposition coverage in the bottom of each via of a semiconductor wafer differs from the coverage in the bottom of each trench of such wafer. The selectivity may be configured so as to result in punch through in each via without damaging the dielectric material at the bottom of each trench or the like. In this configuration, the coverage…
Creation of porosity in low-k films by photo-disassociation of imbedded nanoparticles
Granted: March 31, 2009
Patent Number:
7510982
Porous dielectric layers are produced by embedding and removing nanoparticles in composite dielectric layers. The pores may be produced after the barrier material, the metal or other conductive material is deposited to form a metallization layer. In this manner, the conductive material is provided with a relatively smooth continuous surface on which to deposit.
Apparatus and methods for processing semiconductor substrates using supercritical fluids
Granted: March 17, 2009
Patent Number:
7503334
A system is provided for cleaning wafers that includes specialized pressurization, process vessel, recirculation, chemical addition, depressurization, and recapture-recycle subsystems. A solvent delivery mechanism converts a liquid-state sub-critical solution to a supercritical cleaning solution and introduces it into a process vessel that contains a wafer or wafers. The supercritical cleaning solution is recirculated through the process vessel by a recirculation system. An additive…
Apparatus for reduction of defects in wet processed layers
Granted: March 17, 2009
Patent Number:
7503830
The present invention provides an apparatus for wet processing of a conductive layer using a degassed process solution such as a degassed electrochemical deposition solution, a degassed electrochemical polishing solution, a degassed deposition solution, and a degassed cleaning solution. The technique includes degassing the process solution before delivering the degassed process solution to a processing unit or degassing the process solution in situ, within the processing unit.
Method of making rolling electrical contact to wafer front surface
Granted: February 17, 2009
Patent Number:
7491308
Substantially uniform deposition of conductive material on a surface of a substrate, which substrate includes a semiconductor wafer, from an electrolyte containing the conductive material can be provided by way of a particular device which includes first and second conductive elements. The first conductive element can have multiple electrical contacts, of identical or different configurations, or may be in the form of a conductive pad, and can contact or otherwise electrically…
Metal-free catalysts for pulsed deposition layer process for conformal silica laminates
Granted: February 17, 2009
Patent Number:
7491653
A metal- and metalloid-free nanolaminate dielectric film can be formed according to a pulsed layer deposition (PDL) process. A metal- and metalloid-free compound is used to catalyze the reaction of silica deposition by surface reaction of alkoxysilanols. Films can be grown at rates faster than 30 nm per exposure cycle. The invention can be used for the deposition of both doped (e.g., PSG) and undoped silicon oxide films. The films deposited are conformal, hence the method can accomplish…
Method of forming nitride films with high compressive stress for improved PFET device performance
Granted: February 17, 2009
Patent Number:
7491660
A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is…
Stress profile modulation in STI gap fill
Granted: January 27, 2009
Patent Number:
7482245
High density plasma (HDP) techniques form silicon oxide films having sequentially modulated stress profiles. The HDP techniques use low enough temperatures to deposit silicon oxide films in transistor architectures and fabrication processes effective for generating channel strain without adversely impacting transistor integrity. Methods involve partially filling a trench on a substrate with a portion of deposited dielectric using a high density plasma chemical vapor deposition process.…
Conformal nanolaminate dielectric deposition and etch bag gap fill process
Granted: January 27, 2009
Patent Number:
7482247
Conformal nanolaminate dielectric deposition and etch back processes that can fill high aspect ratio (typically at least 5:1, for example 6:1), narrow width (typically sub 0.13 micron, for example 0.1 micron or less) gaps with significantly reduced incidence of voids or weak spots involve the use of any suitable confirmal dielectric deposition technique and a dry etch back. The etch back part of the process involves a single step or an integrated multi-step (for example, two-step)…
