Method for endpointing CVD chamber cleans following ultra low-k film treatments
Granted: January 20, 2009
Patent Number:
7479191
Methods of determining the endpoint of cleaning residues from the internal surfaces of a chemical vapor deposition chamber are described. The methods are especially useful for determining when organic-based residues deposited from an ultra low-k film precursor deposition are removed from the chamber. The methods involve cleaning the chamber with a plasma comprising fluorine and oxygen while monitoring the intensity of the optical emission lines of one or more atomic or molecular species…
Apparatus for processing surface of workpiece with small electrodes and surface contacts
Granted: January 13, 2009
Patent Number:
7476304
Deposition of conductive material on or removal of conductive material from a workpiece frontal side of a semiconductor workpiece is performed by providing an anode having an anode area which is to face the workpiece frontal side, and electrically connecting the workpiece frontal side with at least one electrical contact, outside of the anode area, by pushing the electrical contact and the workpiece frontal side into proximity with each other. A potential is applied between the anode and…
Halogen-free noble gas assisted Hplasma etch process in deposition-etch-deposition gap fill
Granted: January 13, 2009
Patent Number:
7476621
Plasma etch processes incorporating H2/Noble gas etch chemistries. In particular, high density plasma chemical vapor etch-enhanced (deposition-etch-deposition) gap fill processes incorporating etch chemistries which incorporate hydrogen and one or more Noble gases as the etchant that can effectively fill high aspect ratio gaps while reducing or eliminating dielectric contamination by etchant chemical species.
Apparatus and methods for precompiling program sequences for wafer processing
Granted: January 13, 2009
Patent Number:
7477948
Disclosed are apparatus and methods for embodiments for efficiently and flexibly controlling hardware devices in a semiconductor processing system are provided for use in a distributed control arrangement. In general, the distributed arrangement includes at least one upper-level controller that is configurable with a computer program sequence of instructions for controlling one or more hardware devices of a processing tool. The hardware devices are controlled through one or more…
Methods for producing low stress porous low-k dielectric materials using precursors with organic functional groups
Granted: January 6, 2009
Patent Number:
7473653
Methods of preparing a low stress porous low-k dielectric material on a substrate are provided. The methods involve the use of a structure former precursor and/or porogen precursor with one or more organic functional groups. In some cases, the structure former precursor has carbon-carbon double or triple bonds. In other cases, one or both of the structure former precursor and porogen precursor has one or more bulky organic groups. In other cases, the structure former precursor has…
Methods of multi-step electrochemical mechanical planarization of Cu
Granted: December 23, 2008
Patent Number:
7468322
A method is provided for removing conductive material from a metal layer deposited on a wafer having die level thickness variations on its surface. The method includes contacting the metal layer with a composition capable of planarizing die level thickness variations while using a current having a current density within a range of between about 5 mA/cm2 and about 40 mA/cm2, applying a first current to the wafer having a current density within a range of between about 5 mA/cm2 and about…
Method of forming nitride films with high compressive stress for improved PFET device performance
Granted: December 9, 2008
Patent Number:
7462527
A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is…
Method for enhancing the nucleation and morphology of ruthenium films on dielectric substrates using amine containing compounds
Granted: November 25, 2008
Patent Number:
7456101
Methods for depositing a ruthenium metal layer on a dielectric substrate are provided. The methods involve, for instance, exposing the dielectric substrate to an amine-containing compound, followed by exposing the substrate to a ruthenium precursor and an optional co-reactant such that the amine-containing compound facilitates the nucleation on the dielectric surface.
Electroless copper fill process
Granted: November 25, 2008
Patent Number:
7456102
Disclosed is a procedure for bottom-up fill of electroless copper film in sub-micron integrated circuit features. By repeatedly placing an integrated circuit wafer in an electroless bath, a transient period of time of accelerated growth in the feature is repeated to achieve many small layers of deposition, each of which is thicker near the base of the feature. The net result is filing of the feature from the bottom-up fill without formation of voids. The electroless bath employed to form…
Selectively accelerated plating of metal features
Granted: November 11, 2008
Patent Number:
7449099
To make a metal feature, a non-plateable layer is applied to a workpiece surface and then patterned to form a first plating region and a first non-plating region. Then, metal is deposited on the workpiece to form a raised field region in said first plating region and a recessed region in said first non-plating region. Then, an accelerator film is applied globally on the workpiece. A portion of the accelerator film is selectively removed from the field region, and another portion of the…
Method for planar electroplating
Granted: November 11, 2008
Patent Number:
7449098
A disclosed form of mechanically assisted electroplating leads to a flat, thin, overburden. In one example, an accelerator is deposited on a copper surface and mechanically removed in a simplified CMP-like apparatus. The wafer is then plated in an electrolyte containing little or no accelerating additives.
Methods of providing an adhesion layer for adhesion of barrier and/or seed layers to dielectric films
Granted: November 4, 2008
Patent Number:
7446032
A process for enhancing the adhesion of directly plateable materials to an underlying dielectric is demonstrated, so as to withstand damascene processing. Using diffusion barriers onto which copper can be deposited facilitates conventional electrolytic processing. An ultra-thin adhesion layer is applied to a degassed, pre-cleaned substrate. The degassed and pre-cleaned substrate is exposed to a precursor gas containing the adhesion layer, optionally deposited by a plasma-assisted CVD…
Anneal of ruthenium seed layer to improve copper plating
Granted: October 28, 2008
Patent Number:
7442267
A ruthenium-containing thin film is formed. Typically, the ruthenium-containing thin film has a thickness in a range of about from 1 nm to 20 nm. The ruthenium-containing thin film is annealed in an oxygen-free atmosphere, for example, in N2 forming gas, at a temperature in a range of about from 100° C. to 500° C. for a total time duration of about from 10 seconds to 1000 seconds. Thereafter, copper or other metal is deposited by electroplating or electroless plating onto the annealed…
Method for controlling thickness uniformity of electroplated layers
Granted: October 14, 2008
Patent Number:
7435323
An apparatus which can control thickness uniformity during deposition of conductive material from an electrolyte onto a surface of a semiconductor substrate is provided. The apparatus has an anode which can be contacted by the electrolyte during deposition of the conductive material, a cathode assembly including a carrier adapted to carry the substrate for movement during deposition, and a conductive element permitting electrolyte flow therethrough. A mask lies over the conductive…
Resolving of fluorine loading effect in the vacuum chamber
Granted: October 14, 2008
Patent Number:
7435684
This invention relates to electronic device fabrication processes for making devices such as semiconductor wafers and resolves the fluorine loading effect in the reaction chamber of a HDP CVD apparatus used for forming dielectric layers in high aspect ratio, narrow width recessed features. The fluorine loading effect in the chamber is minimized and wafers are provided having less deposition thickness variations by employing the method using a hydrogen plasma treatment of the chamber and…
System for electropolishing and electrochemical mechanical polishing
Granted: September 23, 2008
Patent Number:
7427337
An apparatus for electropolishing a conductive layer on a wafer using a solution is disclosed. The apparatus comprises an electrode assembly immersed in the solution configured proximate to the conductive layer having a longitudinal dimension extending to at least a periphery of the wafer, the electrode assembly including an elongated contact electrode configured to receive a potential difference, an isolator adjacent the elongated contact electrode, and an elongated process electrode…
Method for monitoring edge exclusion during chemical mechanical planarization
Granted: September 23, 2008
Patent Number:
7428470
A method is provided for measuring edge exclusion on a workpiece that includes a wafer having a film disposed thereon. The method is performed by a CMP system employing a platen and a thickness sensor coupled to the platen and positioned to repeatedly travel a path over the edge of the film during polishing. The method comprises measuring the thickness of the workpiece during selected iterations of the probe path, and establishing from the wafer thickness measurements the length of time…
Electrochemical mechanical processing apparatus
Granted: September 16, 2008
Patent Number:
7425250
A system for electrochemical mechanical polishing of a conductive surface of a wafer is provided. The system includes a wafer holder to hold the wafer and a belt pad disposed proximate to the wafer to polish the conductive surface. Application of a potential difference between conductive surface and an electrode and establishing relative motion between the belt pad and the conductive surface result in material removal from the conductive surface. Electrical contact to the surface is…
Methods of providing an adhesion layer for adhesion of barrier and/or seed layers to dielectric films
Granted: September 16, 2008
Patent Number:
7425506
A process for enhancing the adhesion of directly plateable materials to an underlying dielectric is demonstrated, so as to withstand damascene processing. Using diffusion barriers onto which copper can be deposited facilitates conventional electrolytic processing. An ultra-thin adhesion layer is applied to a degassed, pre-cleaned substrate. The degassed and pre-cleaned substrate is exposed to a precursor gas containing the adhesion layer, optionally deposited by a plasma-assisted CVD…
Compositions and methods of electrochemical removal of material from a barrier layer of a wafer
Granted: September 9, 2008
Patent Number:
7422700
Methods and compositions have been provided for removing barrier layer material from a work piece during an electrochemical mechanical polishing process while protecting a metallization layer of the work piece. The electrochemical planarization composition includes at least one complexing agent capable of complexing with the barrier layer material when exposed to a pH outside of a pH range of greater than about pH 2 and less than about pH 10, a corrosion inhibitor, abrasive particles,…
