AUTOMATICALLY PERFORMING A TRADE-OFF BETWEEN VISUAL QUALITY AND LATENCY DURING RENDERING OF A VIDEO/GRAPHICS SEQUENCE
Granted: August 13, 2015
Application Number:
20150228046
A method includes automatically capturing, through a processor of a data processing device communicatively coupled to a memory, one or more parameter(s) related to a visual quality of rendering of a video frame that is part of a sequence on a display unit communicatively coupled to the processor and one or more parameter(s) related to latency associated with the rendering of the video frame on the display unit. The sequence is a video and/or a graphics sequence. The method also includes…
SYSTEM AND METHOD FOR DYNAMIC FREQUENCY ESTIMATION FOR A SPREAD-SPECTRUM DIGITAL PHASE-LOCKED LOOP
Granted: August 6, 2015
Application Number:
20150222284
A digital phase-and-frequency controller. In one embodiment, the controller includes: (1) a first segment accumulator operable to accumulate errors while an accumulation-selection signal has a first value and (2) a second segment accumulator operable to accumulate errors while said accumulation-selection signal has a second value, and (3) circuitry operable to produce the control signal using the errors accumulated in the first segment accumulator while a use-selection signal has a first…
LOW TAU SYNCHRONIZER FLIP-FLOP WITH DUAL LOOP FEEDBACK APPROACH TO IMPROVE MEAN TIME BETWEEN FAILURE
Granted: August 6, 2015
Application Number:
20150222266
A flip-flop and a method of receiving a digital signal from an asynchronous domain. In one embodiment, the flip-flop includes: (1) a first loop coupled to a flip-flop input and having first and second stable states and (2) a second loop coupled to the first loop and having the first and second stable states, properties of cross-coupled inverters in the first and second loops creating a metastable state skewed toward the first stable state in the first loop and skewed toward the second…
SYSTEM AND METHOD FOR COMPUTING GATHERS USING A SINGLE-INSTRUCTION MULTIPLE-THREAD PROCESSOR
Granted: August 6, 2015
Application Number:
20150221123
Systems for, and methods of, computing gathers for processing on a SIMT processor. In one embodiment, the system includes: (1) a thread group creator executing on a processor and operable to assign ray traces pertaining to a single receiver to threads for execution by a SIMT processor and (2) a memory configured to contain at least some of the threads for execution by the SIMT processor.
SYSTEM AND METHOD FOR ROUTING BUFFERED INTERCONNECTS IN AN INTEGRATED CIRCUIT
Granted: August 6, 2015
Application Number:
20150220675
A system and method for routing a buffered interconnect in an IC from a source cell to a target cell thereof. In one embodiment, the system includes: (1) a path tracer operable to designate the source cell as a current node and construct a path toward the target node by: (1a) defining a boundary about the current node based on a buffer driving length, (1b) trimming the boundary by any blockage therein to yield a candidate area for placing a buffer, (1c) dividing the boundary into line…
SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING SOFTWARE-BASED SCOREBOARDING
Granted: August 6, 2015
Application Number:
20150220341
A system, method, and computer program product are provided for implementing a software-based scoreboarding mechanism. The method includes the steps of receiving a dependency barrier instruction that includes an immediate value and an identifier corresponding to a first register and, based on a comparison of the immediate value to the value stored in the first register, dispatching a subsequent instruction to at least a first processing unit of two or more processing units.
CONTROL FLOW OPTIMIZATION FOR EFFICIENT PROGRAM CODE EXECUTION ON A PROCESSOR
Granted: August 6, 2015
Application Number:
20150220314
A method includes identifying a divergent region of interest (DRI) not including a post dominator node thereof within a control flow graph, and introducing a decision node in the control flow graph such that the decision node post-dominates an entry point of the DRI and is dominated by the entry point. The method also includes redirecting a regular control flow path within the control flow graph from another node previously coupled to the DRI to the decision node, and redirecting a…
INTEGRATED CIRCUIT DETECTION CIRCUIT FOR A DIGITAL MULTI-LEVEL STRAP AND METHOD OF OPERATION THEREOF
Granted: August 6, 2015
Application Number:
20150219697
An integrated circuit (IC) based detection circuit for determining a strap value and a method of detecting a digital strap value. In one embodiment, the detection circuit includes: (1) a first receiver including transistors having first electrical characteristics that define a first threshold for the first receiver, the first receiver operable to generate a first binary digit based on an input signal and the first threshold and (2) a second receiver including transistors having second…
BARYCENTRIC FILTERING FOR MEASURED BIDERECTIONAL SCATTERING DISTRIBUTION FUNCTION
Granted: July 30, 2015
Application Number:
20150213641
The disclosure provides a method of determining reflected irradiance for a surface point on a surface whose reflectance properties are represented by a measured BSDF. Additionally, the disclosure provides a renderer and a computer program product. In one embodiment, the method includes: (1) determining u, v and w coordinates in the measured BSDF for the surface point based on an incoming and an outgoing ray direction, (2) selecting a triangle for barycentric interpolation based on values…
PHASE LOCK LOOP (PLL/FLL) CLOCK SIGNAL GENERATION WITH FREQUENCY SCALING TO POWER SUPPLY VOLTAGE
Granted: July 30, 2015
Application Number:
20150214963
A clock signal generation circuit provides an output clock signal to a digital system. The digital system is powered by a power supply voltage, VDD, that may include transients associated with the impedance of the packaged digital system. The clock signal generation circuit dynamically scales an output clock frequency based on monitored changed to VDD. The output clock frequency may be selected to approximate a maximum (margin-less) system Fmax for the monitored VDD. The average clock…
CLOUD GAMING SYSTEM AND METHOD OF INITIATING A GAMING SESSION
Granted: July 30, 2015
Application Number:
20150209662
A gaming cloud gaming system and a method of initiating a gaming session. One embodiment of the gaming cloud gaming system includes a computing system having: (1) an entry point operable to receive a game session request and generate instructions for establishing a connection between a client and a game server, and (2) a dynamically configurable reverse proxy operable to proxy for the game server and configured to employ the instructions to create a route to a randomly selected port on…
GRAPHICS PROCESSING SUBSYSTEM AND METHOD FOR RECOVERING A VIDEO BASIC INPUT/OUTPUT SYSTEM
Granted: July 30, 2015
Application Number:
20150212890
A graphics processing subsystem and a method for recovering a video basic input/output system (VBIOS). One embodiment of the graphics processing subsystem includes: (1) a memory configured to store a VBIOS, and (2) a processor coupled to the memory and configured to employ a bridge to gain access to the VBIOS and cause the VBIOS to be written to the memory.
SYSTEM AND PROCESSOR FOR IMPLEMENTING INTERRUPTIBLE BATCHES OF INSTRUCTIONS
Granted: July 30, 2015
Application Number:
20150212819
A system, method, and computer program product are provided for scheduling interruptible hatches of instructions for execution by one or more functional units of a processor. The method includes the steps of receiving a batch of instructions that includes a plurality of instructions and dispatching at least one instruction from the batch of instructions to one or more functional units for execution. The method further includes the step of receiving an interrupt request that causes an…
METHODS AND SYSTEMS FOR MAINTENANCE AND CONTROL OF APPLICATIONS FOR PERFORMANCE TUNING
Granted: July 30, 2015
Application Number:
20150212815
Methods and systems for maintenance and control of multiple versions of an application are disclosed. The method includes creating a first version of the application comprising computer-executable instructions and executing the first version of the application. The first version of the application and related performance metrics are stored in a memory. The method includes creating at least one modified version of the application by making changes to the computer-executable instructions…
SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR MULTIPLE STIMULUS SENSORS FOR AN INPUT DEVICE
Granted: July 30, 2015
Application Number:
20150212631
A system, method, and computer program product are provided for sensing input stimulus at an input device. The method includes the steps of configuring an input device comprising a first sensor layer and a second sensor layer to activate the first sensor layer and to deactivate the second sensor layer, where the second sensor layer is layered above the first sensor layer and associated with a stimulus device. When a request to activate the second sensor layer is received, the input…
STYLUS TOOL WITH DEFORMABLE TIP
Granted: July 30, 2015
Application Number:
20150212601
A passive stylus with a deformable tip is described herein. In one embodiment, a thin annular body configured to be hand-held with a chisel shaped tip disposed at the first end of the body is provided. The chisel shaped tip includes a deformable material such that the chisel shaped tip is operable to interface with a touch a sensitive surface with a detectable surface area when a first pressure is exerted on the body and translated to the chisel shaped tip. The chisel shaped tip is…
STYLUS TOOL WITH DEFORMABLE TIP
Granted: July 30, 2015
Application Number:
20150212600
A passive stylus with a deformable tip is described herein. In one embodiment, a thin annular body configured to be hand-held with a tip disposed at the first end of the body is provided. The tip includes a deformable material such that the tip is operable to interface with a touch a sensitive surface with a detectable surface area when a first pressure is exerted on the body and translated to the tip. The tip is operable to interface with the touch sensitive surface with a second…
USER SPACE BASED PERFORMANCE STATE SWITCHING OF A PROCESSOR OF A DATA PROCESSING DEVICE
Granted: July 30, 2015
Application Number:
20150212569
A method includes capturing an interaction of a user of a data processing device therewith at a level of a user space through a process executing on the data processing device, and communicating the captured user interaction as an event from the user space to a kernel space associated with an operating system executing on the data processing device. The method also includes incorporating, through the kernel space, the communicated event as a feedback to an algorithm executing on a…
METHODS AND APPARATUS FOR DEBUGGING LOWEST POWER STATES IN SYSTEM-ON-CHIPS
Granted: July 30, 2015
Application Number:
20150212154
Methods and apparatus for debugging finite state machine are disclosed. The method includes implementing a debug logic circuit and connecting the debug logic circuit to a system on chip (SoC) voltage source. The method includes operating a finite state machine that sequences the SoC from a low power state to a next low power state and generating respective output signals corresponding to the low power states and wherein the finite state machine is connected to Always On voltage source.…
DEGRADATION DETECTOR AND METHOD OF DETECTING THE AGING OF AN INTEGRATED CIRCUIT
Granted: July 30, 2015
Application Number:
20150212149
A degradation detector for an integrated circuit (IC), a method of detecting aging in an IC and an IC incorporating the degradation detector or the method. In one embodiment, the degradation detector includes: (1) an offline ring oscillator (RO) coupled to a power gate and a clock gate, (2) a frozen RO coupled to a clock gate, (3) an online RO and (4) an analyzer coupled to the offline RO, the frozen RO and the online RO and operable to place the degradation detector in a normal state in…
