Three-dimensional memory device containing self-aligned isolation strips and methods for forming the same
Granted: October 22, 2024
Patent Number:
12127406
A semiconductor structure includes an alternating stack of insulating layers and composite layers. Each of the composite layers includes a plurality of electrically conductive word line strips laterally extending along a first horizontal direction and a plurality of dielectric isolation strips laterally extending along the first horizontal direction and interlaced with the plurality of electrically conductive word line strips. Rows of memory openings are arranged along the first…
Bonded assembly containing different size opposing bonding pads and methods of forming the same
Granted: October 22, 2024
Patent Number:
12125814
A bonded assembly of a primary semiconductor die and a complementary semiconductor die includes first pairs of first primary bonding pads and first complementary bonding pads that are larger in area than the first primary bonding pads, and second pairs of second primary bonding pads and second complementary bonding pads that are smaller in area than the second primary bonding pads.
Systems and methods for improving find last good page processing in memory devices
Granted: October 22, 2024
Patent Number:
12124704
A storage device includes a memory die and a controller. The controller identifies a dirty block that was subject to an interrupted I/O operation and performs a coarse inspection of the dirty block. Each iteration of the coarse inspection includes: requesting first bytes of a current page of the dirty block; receiving contents of the first bytes from the at least one memory die; and evaluating a state of the current page based on the contents of the first bytes. The controller also…
Data storage device and method for handling write commands in zoned storage
Granted: October 22, 2024
Patent Number:
12124377
Zoned memory typically requires write commands to be sent from a host to a data storage device in logical block address (LBA) sequential order. Instead of rejecting out-of-order write commands, the data storage device can execute those commands and internally deal with the out-of-order problem. For example, the data storage device can use a special zone logical-to-physical address table, use a temporary zone data buffer, and/or store a data's LBA in a header for later matching.
Non-volatile memory with zoned control for limiting programming for different groups of non-volatile memory cells
Granted: October 15, 2024
Patent Number:
12119065
A non-volatile memory system limits the amount of programming for a first type of group of non-volatile memory cells based on a first parameter such that a maximum number of programming pulses applied to the first type of group of non-volatile memory cells to program to the last data state after the first type of group of non-volatile memory cells completed programming to the other data states is X programming pulses. The non-volatile memory system limits the amount of programming for a…
DRAM-less SSD with HMB cache management
Granted: October 15, 2024
Patent Number:
12118242
The present disclosure generally relates to host memory buffer (HMB) cache management in DRAM-less SSDs. HMB is transient memory and may not always be available. For example, when the link between the data storage device and the host device is not active, the data storage device can't access the HMB. Placing an HMB log in the HMB controller that is disposed in the data storage device provides access to data that would otherwise be inaccessible in the HMB. The HMB log contains any deltas…
Asymmetric time division peak power management (TD-PPM) timing windows
Granted: October 15, 2024
Patent Number:
12118219
A data storage device includes a memory device and a controller. The controller is configured to assert a strobe cycle having a plurality of strobes to the memory device, where a die of the memory device may be associated with one or more strobes of the plurality of strobes. The controller is further configured to determine whether the die of the memory device requires additional power and adjust a strobe length of time of the corresponding strobe when the die of the memory device…
Certificates in data storage devices
Granted: October 15, 2024
Patent Number:
12118103
Disclosed herein is a data storage device. A data port transmits data between a host computer system and the data storage device. A non-volatile storage medium stores encrypted user content data and a cryptography engine connected between the data port and the storage medium uses a cryptographic key to decrypt the encrypted user content data. The access controller generates an authorization request for a manager device. The authorization request comprises a certificate. The certificate…
Open block boundary group programming for non-volatile memory
Granted: October 8, 2024
Patent Number:
12112814
Technology for open block boundary group programming of non-volatile memory such as NAND. The open block boundary group could potentially be read in response to a request from a host for the data stored in the group. In an aspect, the memory system will determine whether programming a group of memory cells in a selected block will result in an open block. If it will not result in an open block, then the memory system uses a first set of programming parameters to program the group.…
Surface mount technology method and magnetic carrier system
Granted: October 8, 2024
Patent Number:
12114435
A method of soldering one or more components to a substrate includes providing a substrate and applying an amount of solder material to the top planar surface of the substrate. One or more electrical components are mounted to the solder material in a predetermined position and orientation. A carrier is provided having one or more magnets embedded therein. The substrate is positioned above the carrier such that each of the one or more magnets is positioned directly below a corresponding…
Non-volatile memory with early dummy word line ramp down after precharge
Granted: October 8, 2024
Patent Number:
12112812
Non-volatile memory cells are programmed by pre-charging channels of unselected non-volatile memory cells connected to a selected data word line, boosting the channels of unselected non-volatile memory cells connected to the selected data word line after the pre-charging and applying a program voltage pulse to selected non-volatile memory cells connected to the selected data word line while boosting. The pre-charging includes applying pre-charge voltages to one set of data word lines and…
High speed multi-level cell (MLC) programming in non-volatile memory structures
Granted: October 8, 2024
Patent Number:
12112800
A method for programming a memory array of a non-volatile memory structure, wherein the memory array comprises a population of MLC NAND-type memory cells, and the method comprises: (1) in a first program pulse, programming selected memory cells according to a first programmable state and a second programmable state, and (2) in a second program pulse, programming the selected memory cells according to a third programmable state.
Write performance by relocation during sequential reads
Granted: October 8, 2024
Patent Number:
12112062
A data storage device includes a non-volatile memory device including a memory block including a number of memory dies, and a controller coupled to the non-volatile memory device. A read command is received from an external device and the controller determines whether a read operation associated with the read command is a sequential read operation. One or more relocation operations are performed in response to determining that the read operation is a sequential read operation. The one or…
Adaptive tuning of memory device clock rates based on dynamic parameters
Granted: October 8, 2024
Patent Number:
12112048
The present disclosure generally relates to improving adaptive tuning of different clock rates of a memory device. Rather than clock rates only being determined off of one parameter such as workload, the clock rates now will be determined using multiple parameters. The tuning may be based on system parameters to allow the system to withstand challenges that arise during the operation. The clock frequency table is maintained in the device controller. The table holds the clock frequency of…
Recognition and report of expected write amplification violation
Granted: October 8, 2024
Patent Number:
12112044
The present disclosure generally relates to recognizing a violation of an expected write amplification (WAF) rate and informing a host device of the violation so that the host device may take corrective action and ensure the data storage device does not reach end of life (EOL) earlier than expected. The host can provide the data storage device with an expected lifetime and may additionally provide a benchmark WAF rate. The data storage device compares the actual WAF rate to the benchmark…
Virtual quality control interpolation and process feedback in the production of memory devices
Granted: October 1, 2024
Patent Number:
12105137
To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during…
Self-aligning heat fins for thermal management
Granted: October 1, 2024
Patent Number:
12108577
A thermal dissipation device for use with electronic assemblies or devices and that includes a heat conductive plate configured to thermally couple to one or more packaged components on a first side of the heat conductive plate. The thermal dissipation device further includes a heat conductive post coupled to a second side of the heat conductive plate. The heat conductive post includes a fin member rotatably coupled to the heat conductive post, which is configured to rotate about an axis…
Parallel fragmented SGL fetching for hiding host turnaround time
Granted: October 1, 2024
Patent Number:
12105990
The present disclosure generally relates to reducing latency when fetching Scatter Gather Lists (SGL). Rather than fetching the required SGLs sequentially regardless of what SGL descriptor is needed, the data storage device fetches all of the last entries of each SGL segment in ahead of time after receiving the command, but before the read data is available. The data storage device will still fetch the previous entries in the segment. Once the last entries are fetched, the last entries…
NAND string read voltage adjustment
Granted: October 1, 2024
Patent Number:
12105963
An apparatus includes a control circuit configured to connect to NAND strings that are connected to bit lines, where each bit line is connected to a plurality of NAND strings in a corresponding plurality of regions of a block. The control circuit is configured to apply a read voltage in read operations directed to NAND strings of the plurality of regions of the block and subsequently adjust the read voltage by a first predetermined amount for read operations directed to NAND strings of a…
Data storage with real time dynamic clock frequency control
Granted: October 1, 2024
Patent Number:
12105574
The present disclosure generally relates to ensuring a data storage device consumes as little power as possible. Different HW modules in the data storage device can operate at different frequencies to ensure any bottleneck HW modules operate at as fast a frequency as possible, while non-bottleneck HW modules operate at slower frequencies and hence, consume less power. The frequency for each HW modules is dynamic and is adjusted based upon detected bottlenecks so that the data storage…
