Three-dimensional memory device including an isolation-trench etch stop layer and methods for forming the same
Granted: December 3, 2024
Patent Number:
12160989
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, memory opening fill structures located within a respective one of the memory openings, and a drain-select-level isolation structure. One of the insulating layers is a composite insulating layer including an insulating-material-containing sublayer consisting essentially of an insulating material and an…
Method of forming a semiconductor device including vertical contact fingers
Granted: November 26, 2024
Patent Number:
12154860
A method of forming a semiconductor device includes forming vertical contact fingers in a substrate having side portions that are flexible. Contact fingers are formed near one or more edges of the flexible side portions of the substrate. After semiconductor dies are mounted to and electrically coupled to the substrate, the semiconductor device may be encapsulated by placing the device in a mold chase including upper and lower mold plates. The lower mold plate is sized smaller than the…
Non-volatile memory with tuning of erase process
Granted: November 26, 2024
Patent Number:
12154630
In order to achieve tight and uniform erased threshold voltage distributions in a non-volatile memory system that includes non-volatile memory cells arranged in blocks that have multiple sub-blocks and has an erase process using gate induced drain leakage (GIDL) to generate charge carriers that change threshold voltage of the memory cells, the magnitude of the GIDL is adjusted separately for the sub-blocks.
Accelerator queue in data storage device
Granted: November 26, 2024
Patent Number:
12153831
Disclosed are systems and methods for accelerating commands from accelerators in data storage devices using accelerator queues. A data storage device includes accelerator interfaces, each accelerator interface couples a controller to a respective accelerator. The device also includes a device memory comprising one or more memories and one or more sets of queues. Each set of queues corresponds to a respective memory, at least one queue is configured to queue one or more tasks associated…
Data storage device and method for scanning memory blocks
Granted: November 26, 2024
Patent Number:
12153804
Some areas (e.g., boundary wordlines) in a block of memory can be more error prone than others. Typically, errors in these areas are not detected until after the entire block is programmed. Handling such errors then can result in performance penalties and large data relocations. With the embodiments presented herein, a two-stage programming operation is provided. In the first stage, only the error-prone areas of the block are programmed, and a check is made to determine if an error…
Non-volatile memory with optimized operation sequence
Granted: November 26, 2024
Patent Number:
12153801
A non-volatile memory system separately performs a memory operation for multiple sub-blocks of a block in order from previously determined slowest sub-block of the block to a previously determined faster sub-block of the block. As a slower sub-block is more likely to fail, this order of is more likely to identify a failure earlier in the process thereby saving time and reducing potential for a disturb. In some embodiments, the proposed order of operation can be used in conjunction with a…
Early detection of programming failure for non-volatile memory
Granted: November 19, 2024
Patent Number:
12148489
An apparatus is provided that includes a block including a word line coupled to a plurality of memory cells, and a control circuit coupled to the word line. The control circuit is configured to program the plurality of memory cells by applying program pulses to the word line in a plurality of program loops, determining a first count of a number of the program loops used to complete programming a first subset of the plurality of memory cells to a first programmed state, first comparing…
Memory device including mixed oxide charge trapping materials and methods for forming the same
Granted: November 19, 2024
Patent Number:
12150302
A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening fill structure including a vertical semiconductor channel and a memory film. The memory film includes a tunneling dielectric layer in contact with the vertical semiconductor channel, a first vertical stack of first dielectric oxide material portions located at levels of the insulating layers and including a dielectric oxide material of a first…
Three-dimensional memory device including contact via structures for multi-level stepped surfaces and methods for forming the same
Granted: November 19, 2024
Patent Number:
12150300
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers containing a terrace region having a plurality of steps, memory stack structures extending through the alternating stack, a retro-stepped dielectric material portion overlying the terrace region, first laterally isolated contact structures including a respective first contact via structure and a respective first dielectric spacer, and second laterally isolated contact…
Three-dimensional memory device containing bridges for enhanced structural support and methods of forming the same
Granted: November 19, 2024
Patent Number:
12148710
A three-dimensional memory device includes a first alternating stack of first word lines and first insulating layers, first memory stack structures vertically extending through the first alternating stack, a second alternating stack of second word lines and second insulating layers, second memory stack structures vertically extending through the second alternating stack, plural backside trench fill structures located between the first alternating stack and the second alternating stack,…
Erase method for non-volatile memory with multiple tiers
Granted: November 19, 2024
Patent Number:
12148478
A non-volatile memory system comprises a plurality of non-volatile memory cells divided into three or more tiers. The memory cells can be programmed, erased and read. In order to achieve uniform erase speed for the three or more tiers, the erase process comprises applying a larger voltage bias to control gates of non-volatile memory cells in the outer tiers than the voltage bias applied to control gates of non-volatile memory cells in one or more inner tiers.
Cross-point array IHOLD read margin improvement
Granted: November 19, 2024
Patent Number:
12148459
Technology for read in a cross-point memory array. Drive transistors pass read and write currents to the cross-point memory array. The read current charges a selected word line to turn on a threshold switching selector of a selected memory cell. While the threshold switching selector is on, the current (read or write) passes through the selected memory cell. The memory system applies a smaller overdrive voltage to a drive transistor when the drive transistor is passing the read current…
Ranking images in an image group
Granted: November 19, 2024
Patent Number:
12148245
Systems, methods, and data storage devices for image grouping in an end user device using trained machine learning group classifiers are described. The end user device may include an image group classifier configured to classify new image data objects using an image classification algorithm and set of machine learning parameters previously trained for a specific image group. The end user device may determine embeddings that quantify features of the target image object and use those…
Management of host file-system defragmentation in a data storage device
Granted: November 19, 2024
Patent Number:
12147704
A data storage device having a flash translation layer configured to handle file-system defragmentation in a manner that avoids, reduces, and/or optimizes physical data movement in flash memory. In an example embodiment, the memory controller maintains in a volatile memory thereof a lookaside table that supplants pertinent portions of the logical-to-physical table. Entries of the lookaside table are configured to track source and destination addresses of the host defragmentation requests…
Non-volatile memory with adapting erase process
Granted: November 19, 2024
Patent Number:
12147695
A memory system performs an erase process for the non-volatile memory cells including performing erase verify for the non-volatile memory cells. The erase verify comprises comparing threshold voltages of the non-volatile memory cells to an erase verify reference voltage and determining whether an amount of the non-volatile memory cells having a threshold voltage greater than the erase verify reference voltage is less than an allowed bit count. During the erase process, the system…
Method of making ovonic threshold switch selectors using microwave annealing
Granted: November 12, 2024
Patent Number:
12144185
A method includes forming a first electrode layer over a substrate, forming an ovonic threshold switch (OTS) material layer over the first electrode layer, microwave annealing the OTS material layer, and forming a second electrode layer over the OTS material layer.
Monolithic surface mount passive component
Granted: November 12, 2024
Patent Number:
12142402
A data storage device includes a substrate including a number of contact pads and a number of passive component packages coupled to the contact pads. The data storage device further includes a memory controller coupled to the substrate, and one or more NAND die stacks coupled to the substrate and in electrical communication with the memory controller. One or more of the passive component packages include a first passive component, a second passive component electrically connected to the…
Foggy-fine drain-side select gate re-program for on-pitch semi-circle drain side select gates
Granted: November 12, 2024
Patent Number:
12142323
A memory apparatus and method of operation are provided. The apparatus includes drain-side select gate transistors for coupling to a drain-side of memory holes of memory cells and configured to retain a transistor threshold voltage. The memory holes are arranged in rows comprising strings. A control means is configured to program drain-side select gate transistors of the memory holes to an initial transistor threshold voltage using pulses increasing in magnitude by a first transistor…
Generalized verification scheme for safe metadata modification
Granted: November 12, 2024
Patent Number:
12141123
System and method of verifying validity of a metadata modification request to prevent improper metadata operations. During initialization of a volume in a storage device and once a metadata area is reserved for a metadata structure, information characterizing the metadata structure and metadata area is stored in the storage device, which may be in the form of an area legend composed of descriptors such as a magic signature, a node size, a clump size of reservation, and extent of the…
Folding zone management optimization in storage device
Granted: November 5, 2024
Patent Number:
12135904
A data storage device for providing zone management optimization may include memories including staging memory areas (e.g., single level cells) and destination memory areas (e.g., quad-level cells). The destination memory areas may include memory regions (e.g., zones). A controller may be configured to receive data from a host system, write the data initially to the staging memory areas, receive a region full indication for a first memory region. In response to receiving the region full…
