Three-dimensional memory device with vertical word line barrier and methods for forming the same
Granted: November 5, 2024
Patent Number:
12137565
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located within the memory openings. Each of the electrically conductive layers includes a metallic fill material layer and a plurality of vertical tubular metallic liners laterally surrounding a respective one of the memory opening fill structures and located between…
Three-dimensional memory device with word-line etch stop liners and method of making thereof
Granted: November 5, 2024
Patent Number:
12137554
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, etch stop plates located in the staircase region, laterally and vertically spaced apart among one another, and overlying an end portion of a respective one of the electrically conductive layers, and contact via structures located in a staircase region, vertically…
Storage-free message authenticators for error-correcting-codes
Granted: November 5, 2024
Patent Number:
12137164
Techniques for storage-free message authentication for error-correcting-codes are disclosed. A storage controller of a storage device receives a request to encode a message in a format having an error-correcting code schema that generates a parity code. A key generator generates a pseudorandom transposition of the message and the parity code as a first part of a secret key. A pseudorandom character string is determined as a second part of the secret key. The output of the pseudorandom…
Storage system and method for improving read latency during mixed read/write operations
Granted: November 5, 2024
Patent Number:
12136462
A storage system receives a request to read data that is located in a wordline undergoing a program operation. Instead of waiting for the program operation to complete, which would increase read latency, the storage system aborts the program operation and reconstructs the data from successfully-programmed memory cells in the wordline and from data latches associated with unsuccessfully-programmed memory cells in the wordline. The reconstructed data is then sent to the host. The program…
Image group classifier in a user device
Granted: November 5, 2024
Patent Number:
12136293
Systems, methods, and data storage devices for image grouping in an end user device using trained machine learning group classifiers are described. The end user device may include an image group classifier configured to classify new image data objects using an image classification algorithm and set of machine learning parameters previously trained for a specific image group. The end user device may determine embeddings that quantify features of the target image object and use those…
Folding zone management optimization in storage device
Granted: November 5, 2024
Patent Number:
12135904
A data storage device for providing zone management optimization may include memories including staging memory areas (e.g., single level cells) and destination memory areas (e.g., quad-level cells). The destination memory areas may include memory regions (e.g., zones). A controller may be configured to receive data from a host system, write the data initially to the staging memory areas, receive a region full indication for a first memory region. In response to receiving the region full…
Protocol indicator for data transfer
Granted: October 29, 2024
Patent Number:
12130766
Systems and methods are disclosed for providing an indication of the data transfer protocol that is operative during a data transfer operation between a data storage device capable of supporting a plurality of data transfer protocols and a host computer. A protocol controller of the data storage device is configured to determine a data transfer protocol based on a data cable used and to generate a selector signal used to provide the indication.
Three-dimensional memory device with self-aligned etch stop rings for a source contact layer and method of making the same
Granted: October 29, 2024
Patent Number:
12133388
A memory device includes a lower source-level semiconductor layer, a source contact layer, an upper source-level semiconductor layer, and an alternating stack of insulating layers and electrically conductive layers, and a memory opening fill structure vertically extending through the alternating stack and down to an upper portion of the lower source-level semiconductor layer. The memory opening fill structure includes a vertical semiconductor channel, a memory film laterally surrounding…
Three-dimensional memory device with contact via structures located over support pillar structures and method of making thereof
Granted: October 29, 2024
Patent Number:
12133382
An alternating stack of insulating layers and sacrificial material layers is formed over a substrate, and support pillar structures are formed through the alternating stack. Stepped surfaces are formed by patterning the alternating stack and the support pillar structures. A retro-stepped dielectric material portion is formed over the stepped surfaces. Memory openings and memory opening fill structures are formed through the alternating stack. Electrically conductive layers are formed by…
Configurable arithmetic HW accelerator
Granted: October 29, 2024
Patent Number:
12131058
A data storage device includes a memory device and a controller coupled to the memory device. The controller includes a decoder multiplexer (mux) module, a plurality of request/response channels coupled to the decoder mux module, an arithmetic pipeline module coupled to the plurality of request/response channels, an arbiter module coupled to the plurality of request/response channels and the arithmetic pipeline module, a mux/arbiter module coupled to the arithmetic pipeline module, a…
Memory device including a ferroelectric semiconductor channel and methods of forming the same
Granted: October 22, 2024
Patent Number:
12127410
A memory device includes a ferroelectric semiconductor channel, a source region contacting a first portion of the ferroelectric semiconductor channel, a drain region located above the source region and contacting a second portion of the ferroelectric semiconductor channel located above the first portion, a word line, and a gate dielectric located between the word line and the ferroelectric semiconductor channel.
Three-dimensional memory device containing self-aligned isolation strips and methods for forming the same
Granted: October 22, 2024
Patent Number:
12127406
A semiconductor structure includes an alternating stack of insulating layers and composite layers. Each of the composite layers includes a plurality of electrically conductive word line strips laterally extending along a first horizontal direction and a plurality of dielectric isolation strips laterally extending along the first horizontal direction and interlaced with the plurality of electrically conductive word line strips. Rows of memory openings are arranged along the first…
Bonded assembly containing different size opposing bonding pads and methods of forming the same
Granted: October 22, 2024
Patent Number:
12125814
A bonded assembly of a primary semiconductor die and a complementary semiconductor die includes first pairs of first primary bonding pads and first complementary bonding pads that are larger in area than the first primary bonding pads, and second pairs of second primary bonding pads and second complementary bonding pads that are smaller in area than the second primary bonding pads.
Systems and methods for improving find last good page processing in memory devices
Granted: October 22, 2024
Patent Number:
12124704
A storage device includes a memory die and a controller. The controller identifies a dirty block that was subject to an interrupted I/O operation and performs a coarse inspection of the dirty block. Each iteration of the coarse inspection includes: requesting first bytes of a current page of the dirty block; receiving contents of the first bytes from the at least one memory die; and evaluating a state of the current page based on the contents of the first bytes. The controller also…
Data storage device and method for handling write commands in zoned storage
Granted: October 22, 2024
Patent Number:
12124377
Zoned memory typically requires write commands to be sent from a host to a data storage device in logical block address (LBA) sequential order. Instead of rejecting out-of-order write commands, the data storage device can execute those commands and internally deal with the out-of-order problem. For example, the data storage device can use a special zone logical-to-physical address table, use a temporary zone data buffer, and/or store a data's LBA in a header for later matching.
Implementation of deep neural networks for testing and quality control in the production of memory devices
Granted: October 22, 2024
Patent Number:
12124247
Techniques are presented for the application of neural networks to the fabrication of integrated circuits and electronic devices, where example are given for the fabrication of non-volatile memory circuits and the mounting of circuit components on the printed circuit board of a solid state drive (SSD). The techniques include the generation of high precision masks suitable for analyzing electron microscope images of feature of integrated circuits and of handling the training of the neural…
Nucleic acid sequencing by synthesis using magnetic sensor arrays
Granted: October 22, 2024
Patent Number:
12121896
Disclosed herein are apparatuses for nucleic acid sequencing, and methods of making and using such apparatuses. In some embodiments, the apparatus comprises a magnetic sensor array comprising a plurality of magnetic sensors, each of the plurality of magnetic sensors coupled to at least one address line, at least one selector element, and a fluid chamber adjacent to the magnetic sensor array, the fluid chamber having a proximal wall adjacent to the magnetic sensor array. A method of…
Certificates in data storage devices
Granted: October 15, 2024
Patent Number:
12118103
Disclosed herein is a data storage device. A data port transmits data between a host computer system and the data storage device. A non-volatile storage medium stores encrypted user content data and a cryptography engine connected between the data port and the storage medium uses a cryptographic key to decrypt the encrypted user content data. The access controller generates an authorization request for a manager device. The authorization request comprises a certificate. The certificate…
DRAM-less SSD with HMB cache management
Granted: October 15, 2024
Patent Number:
12118242
The present disclosure generally relates to host memory buffer (HMB) cache management in DRAM-less SSDs. HMB is transient memory and may not always be available. For example, when the link between the data storage device and the host device is not active, the data storage device can't access the HMB. Placing an HMB log in the HMB controller that is disposed in the data storage device provides access to data that would otherwise be inaccessible in the HMB. The HMB log contains any deltas…
Asymmetric time division peak power management (TD-PPM) timing windows
Granted: October 15, 2024
Patent Number:
12118219
A data storage device includes a memory device and a controller. The controller is configured to assert a strobe cycle having a plurality of strobes to the memory device, where a die of the memory device may be associated with one or more strobes of the plurality of strobes. The controller is further configured to determine whether the die of the memory device requires additional power and adjust a strobe length of time of the corresponding strobe when the die of the memory device…
