Host queues recovery in exception flows
Granted: March 11, 2025
Patent Number:
12248703
In some exception flows, a device controller may need to store and subsequently recover a current state of a host queue. In these particular exception flows, recovering the current state of the host queue is complex due to the varying states a host queue may be in at the time of storing, including having pending commands in the host queue. Examples of such exception flows include low power modes in client SSDs and live migrations in enterprise SSDs. Using dummy host submission and…
Data storage device and method for reducing read disturbs when reading redundantly-stored data
Granted: March 11, 2025
Patent Number:
12248685
A data storage device and method for reducing read disturbs when reading redundantly-stored data are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The memory is configured to redundantly store a plurality of copies of data, wherein the plurality of copies of the data comprise a primary copy of the data and at least one secondary copy of the data. The controller is configured to randomly select one of the plurality of copies of the…
Storage optimization of CAT table during background operations
Granted: March 11, 2025
Patent Number:
12248676
A data storage device includes a memory device, a random access memory (RAM) device, and a controller coupled to the memory device and the RAM device. The controller is configured to determine a workload type of the data storage device, determine to store at least a portion of a compressed logical to physical translation table (ZCAT) in the RAM device based on the workload type, and utilize a remaining portion of the RAM device to perform background operations. The controller is further…
Record and playback commands for storage devices
Granted: March 11, 2025
Patent Number:
12248397
Methods for recording commands in memory and providing the recorded commands. In one embodiment, a data storage controller includes a memory interface configured to interface with a memory, a controller memory including a storage firmware and a record mapping table, and a processor. The processor, when executing the storage firmware, is configured to receive a record identifier, receive a command including data to be stored in the memory, and create an entry in the record mapping table…
Data storage device and method for predictable low-latency in a time-sensitive environment
Granted: March 11, 2025
Patent Number:
12248395
A data storage device and method are provided for predictable low-latency in a time-sensitive environment. In one embodiment, a data storage device is provided comprising a memory and a controller configured to communicate with the memory. The controller is further configured to: receive, from a host, an indication of a logical block address range that the host will later read; and in response to receiving the indication: read data from the logical block address range; and perform an…
Data storage device and method for enhanced recovery through a hardware reset of one of its discrete components
Granted: March 11, 2025
Patent Number:
12248373
A data storage device and method for enhanced recovery through data storage device discrete-component-hardware-reset are provided. In one embodiment, the data storage device determines that a subset of a plurality of memory dies is non-responsive, sends a request to a host to accept longer delays associated with the subset of the plurality of memory dies, power-cycles the subset of the plurality of memory dies, and then informs the host that the latency associated with those dies has…
Solid-state device with multi-tier extreme thermal throttling
Granted: March 11, 2025
Patent Number:
12248345
Aspects of a storage device are provided that apply advanced thermal throttling with multi-tier extreme thermal throttling. Initially, a controller determines whether a first temperature measurement indicates that a temperature of the memory meets a first thermal threshold associated with a first-tier extreme thermal throttling or a second thermal threshold associated with a second-tier extreme thermal throttling. Subsequently, the controller enables the first-tier extreme thermal…
Bonded semiconductor die assembly containing through-stack via structures and methods for making the same
Granted: March 4, 2025
Patent Number:
12243865
A bonded assembly includes a first three-dimensional memory die containing a first alternating stack of first insulating layers and first electrically conductive layers and first memory structures located in the first alternating stack, a second three-dimensional memory die bonded to the first three-dimensional memory die, and containing a second alternating stack of second insulating layers and second electrically conductive layers, and second memory structures located in the second…
Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings
Granted: March 4, 2025
Patent Number:
12245434
A method includes forming an alternating stack of first and second layers, forming a composite hard mask layer over the alternating stack, forming openings in the hard mask, and forming via openings through the alternating stack by performing an anisotropic etch process that transfers a pattern of the openings in the composite hard mask layer through the alternating stack. The compositing hard mask includes a first cladding material layer which has higher etch resistance than upper and…
Three dimensional memory device containing resonant tunneling barrier and high mobility channel and method of making thereof
Granted: March 4, 2025
Patent Number:
12245425
A three-dimensional memory device containing a plurality of levels of memory elements includes a memory film containing a layer stack that includes a resonant tunneling barrier stack, a semiconductor barrier layer, and a memory material layer located between the resonant tunneling barrier stack and the semiconductor barrier layer, a semiconductor channel, and a control gate electrode.
Data storage device configured for use with a generative-adversarial-network (GAN)
Granted: March 4, 2025
Patent Number:
12242345
Data storage devices configured to exploit generative-adversarial-networks (GANs). The GANs include super-resolution GANs (SRGANS). In some examples, a GAN-based decoding reconstruction procedure is implemented within a data storage controller to replace or supplement an error correction coding (ECC) decoding procedure. In other examples, soft bit information is exploited using GANs during decoding. A dissimilarity matrix may be generated to represent differences between an initial image…
Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings
Granted: March 4, 2025
Patent Number:
12243776
A source-level semiconductor layer and an alternating stack of first material layers and second material layers is formed above a substrate. A hard mask layer is formed over the alternating stack, and is subsequently patterned to provide a pattern of cavities therethrough. Via openings are formed through the alternating stack by performing an anisotropic etch process. A cladding liner is formed on sidewalls of the cavities in the hard mask layer and on a top surface of the hard mask…
Low power read method and a memory device capable thereof
Granted: March 4, 2025
Patent Number:
12243593
The memory device includes a chip with circuitry, a plurality of memory blocks, and a plurality of bit lines. The memory blocks include an array of memory cells, and the circuitry either overlies or underlies the array of memory cells. The bit lines are divided into two portions that are electrically connected with one another via at least one transistor so that at least one portion of each bit line can be charged independently of the other portion of the same bit line.
In-place write techniques without erase in a memory device
Granted: March 4, 2025
Patent Number:
12243591
The memory device includes a plurality of memory blocks, each including a plurality of memory cells arranged in a plurality of word lines. Control circuitry is in communication with the plurality of memory blocks. In operation, the control circuitry receives a data write instruction and programs the memory cells of the memory blocks to a one bit per memory cell (SLC) format. In response to the data programmed to the memory cells of the memory blocks in the SLC format reaching an SLC…
Automatic data erase from data storage device
Granted: March 4, 2025
Patent Number:
12242754
A data storage device comprising a non-volatile storage medium configured to store user data, a data port configured to receive and transmit data between a host computer system and the data storage device, and a controller. The controller is configured to receive, via the data port, a write command comprising a read restriction indication, receive, via the data port, data and write the data to an address of the non-volatile storage medium. The controller is further configured to…
Performance indicator on a data storage device
Granted: March 4, 2025
Patent Number:
12242752
A data storage device comprising a non-volatile storage medium configured to store user data, a data port configured to transmit data between a host computer system and the data storage device, a display system, and a controller. The controller is configured to receive and execute one or more commands from the host computer system to cause a data transfer between the host computer system and the storage medium of the data storage device. The controller generates performance data…
Data storage device and method for host-assisted efficient handling of multiple versions of data
Granted: March 4, 2025
Patent Number:
12242751
A data storage device and method for host-assisted efficient handling of multiple versions of data are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to receive, from a host, identification of different versions of data that are to deleted together, store the different versions of the data in areas of the memory that are erasable in parallel; receive, from the host, a command to erase the different…
Data storage device and method for hiding tweak generation latency
Granted: March 4, 2025
Patent Number:
12242740
A data storage device has a controller, a decryption engine, and a memory storing encrypted data. Instead of using the decryption engine to generate a tweak value needed to decrypt the encrypted data, the tweak value is generated by the controller while the controller is waiting for the encrypted data to be read from the memory. This hides the latency to compute the tweak value in the latency to read the encrypted data from the memory.
Data storage device and method for accident-mode storage of vehicle information
Granted: March 4, 2025
Patent Number:
12242737
A data storage device and method for accident-mode storage of vehicle information are disclosed. In one embodiment, a data storage device is provided comprising a memory and one or more processors. The memory comprises single-level cell (SLC) memory and multi-level cell (MLC) memory. The one or more processors, individually or in combination, are configured to: receive a command from a vehicle to enter accident mode; and in response to receiving the command from the vehicle to enter…
Data storage device management system
Granted: March 4, 2025
Patent Number:
12242378
Devices and techniques are disclosed wherein an end user can remotely trigger direct data management activities of a data storage device (DSD), such as creating a data snapshot, resetting a snapshot, and setting permissions at the DSD via a remote mobile device app interface.
