Three-dimensional memory device containing auxiliary support pillar structures and method of making the same
Granted: April 25, 2023
Patent Number:
11637118
A alternating stack of insulating layers and sacrificial material layers is formed over a substrate. An array of memory opening fill structures and an array of support pillar structures are formed through the alternating stack. Backside trenches are formed through the alternating stack by performing an anisotropic etch process. The anisotropic etch process etches peripheral portions of a subset of the array of support pillar structures. The sacrificial material layers are replaced with…
Three-dimensional memory device containing self-aligned lateral contact elements and methods for forming the same
Granted: April 25, 2023
Patent Number:
11637038
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers having stepped surfaces, memory stack structures extending through the alternating stack, a retro-stepped dielectric material portion overlying the stepped surfaces, and pillar-shaped contact-opening assemblies located within a respective pillar-shaped volume vertically extending through the retro-stepped dielectric material portion and a region of the alternating stack…
Temperature compensation for unselected sub-block inhibit bias for mitigating erase disturb
Granted: April 25, 2023
Patent Number:
11636905
A memory apparatus and method of operation is provided. The apparatus includes a block having memory cells connected to word lines and arranged in strings and is divided into a first sub-block and a second sub-block each configured to be erased as a whole in an erase operation. The apparatus has a temperature measuring circuit configured to detect an ambient temperature of the apparatus. A control circuit is configured to determine a word line inhibit voltage based on the ambient…
Three-dimensional memory device including discrete charge storage elements and methods of forming the same
Granted: April 18, 2023
Patent Number:
11631696
An alternating stack of disposable material layers and silicon nitride layers is formed over a substrate. Memory openings are formed through the alternating stack, and memory opening fill structures are formed in the memory openings, wherein each of the memory opening fill structures comprises a charge storage material layer, a tunneling dielectric layer, and a vertical semiconductor channel Laterally-extending cavities are formed by removing the disposable material layers selective to…
Three-dimensional memory device containing composite word lines containing metal and silicide and method of making thereof
Granted: April 18, 2023
Patent Number:
11631695
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. Each electrically conductive layer within a subset of the electrically conductive layers includes a respective first metal layer containing an elemental metal and a respective first metal silicide layer containing a metal silicide of the elemental metal. Memory openings vertically extend through the alternating stack. Memory opening fill…
Three-dimensional flat memory device including a dual dipole blocking dielectric layer and methods of making the same
Granted: April 18, 2023
Patent Number:
11631691
A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips located over a substrate and laterally spaced apart among one another by line trenches which laterally extend along a first horizontal direction and are spaced apart along a second horizontal direction, and memory stack structures arranged in rows extending along the first horizontal direction. Each row of memory stack structures is located on a respective sidewall of the…
Three-dimensional memory device including trench-isolated memory planes and method of making the same
Granted: April 18, 2023
Patent Number:
11631690
A three-dimensional memory device includes a first three-dimensional memory plane including first alternating stacks of first insulating layers and first word lines, and first bit lines electrically connected first vertical semiconductor channels, and a second three-dimensional memory plane including second alternating stacks of second insulating layers and second word lines and second bit lines electrically connected to second vertical channels. An inter-array backside trench laterally…
Three-dimensional memory array including dual work function floating gates and method of making the same
Granted: April 18, 2023
Patent Number:
11631686
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory opening fill structures extending through the alternating stack, where each of the memory opening fill structures includes a vertical semiconductor channel, a tunneling dielectric layer, and a vertical stack of memory elements located at levels of the electrically conductive layers between a respective vertically neighboring pair of the insulating layers. Each…
Three-dimensional memory device with plural channels per memory opening and methods of making the same
Granted: April 11, 2023
Patent Number:
11626418
A three-dimensional memory device includes an alternating stacks of insulating layers and electrically conductive layers. Memory opening fill structures located in memory openings include a memory film and plural vertical semiconductor channels.
High voltage field effect transistors with self-aligned silicide contacts and methods for making the same
Granted: April 11, 2023
Patent Number:
11626496
A field effect transistor includes a source region and a drain region formed within and/or above openings in a dielectric capping mask layer overlying a semiconductor substrate and a gate electrode. A source-side silicide portion and a drain-side silicide portion are self-aligned to the source region and to the drain region, respectively.
Lateral transistors for selecting blocks in a three-dimensional memory array and methods for forming the same
Granted: April 11, 2023
Patent Number:
11626415
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory opening fill structures including a respective vertical semiconductor channel and a respective vertical stack of memory elements extending through the alternating stack in a memory array region, via contact structures contacting the stepped surfaces of the electrically conductive layers at each step in a staircase region, and a vertical stack of access…
Gate material-based capacitor and resistor structures and methods of forming the same
Granted: April 11, 2023
Patent Number:
11626397
At least one of a capacitor or a resistor structure can be formed concurrently with formation of a field effect transistor by patterning a gate dielectric layer into gate dielectric and into a first node dielectric or a first resistor isolation dielectric, and by patterning a semiconductor layer into a gate electrode and into a second electrode of a capacitor or a resistor strip. Contacts are then formed to the capacitor or resistor structure. Sidewall spacers may be formed on the gate…
Dynamic sense node voltage to compensate for variances when sensing threshold voltages of memory cells
Granted: April 11, 2023
Patent Number:
11626160
Technology for sensing non-volatile memory cells in which one or more sense nodes are charged to a sense voltage having a magnitude that improves sensing accuracy. One sense node may be charged to different sense voltages when sensing different memory cells at different times. Multiple sense nodes may be charged to a corresponding multiple different sense voltages when sensing different memory cells at the same time. The one or more sense nodes are allowed to discharge based on…
Realization of neural networks with ternary inputs and ternary weights in NAND memory arrays
Granted: April 11, 2023
Patent Number:
11625586
Use of a NAND array architecture to realize a binary neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a BNN is stored in a pair of series connected memory cells. A binary input is applied on a pair of word lines connected to the unit synapse to perform the multiplication of the input with the weight. The results of such multiplications are determined by a sense amplifier, with the…
Programming memory cells with concurrent redundant storage of data for power loss protection
Granted: April 11, 2023
Patent Number:
11625172
Apparatuses and techniques are described for programming data in memory cells while concurrently storing backup data. One or more initial pages of data are programmed into both a primary block and a first backup block in a first program pass. A power loss then occurs which can corrupt the data or otherwise prevent reading of the one or more initial pages of data from the primary block. The one or more initial pages of data are read from the first backup block and used to perform a second…
Bipolar electrode bubble detection method and apparatus
Granted: April 4, 2023
Patent Number:
11619604
A bubble detection method includes flowing a fluid through a conduit containing at least one bipolar electrode, applying an electric field across the fluid in the conduit, and detecting a presence of a bubble in the fluid when the bubble flows around or through the bipolar electrode by detecting a current or voltage output from the at least one bipolar electrode.
Multilevel memory stack structure with tapered inter-tier joint region and methods of making thereof
Granted: April 4, 2023
Patent Number:
11621277
A joint level dielectric material layer is formed over a first alternating stack of first insulating layers and first spacer material layers. A first memory opening is formed with a tapered sidewall of the joint level dielectric material layer. A second alternating stack of second insulating layers and second spacer material layers is formed over the joint level dielectric material layer. An inter-tier memory opening is formed, which includes a volume of an second memory opening that…
Bipolar electrode bubble detection method and apparatus
Granted: April 4, 2023
Patent Number:
11619604
A bubble detection method includes flowing a fluid through a conduit containing at least one bipolar electrode, applying an electric field across the fluid in the conduit, and detecting a presence of a bubble in the fluid when the bubble flows around or through the bipolar electrode by detecting a current or voltage output from the at least one bipolar electrode.
Multilevel memory stack structure with tapered inter-tier joint region and methods of making thereof
Granted: April 4, 2023
Patent Number:
11621277
A joint level dielectric material layer is formed over a first alternating stack of first insulating layers and first spacer material layers. A first memory opening is formed with a tapered sidewall of the joint level dielectric material layer. A second alternating stack of second insulating layers and second spacer material layers is formed over the joint level dielectric material layer. An inter-tier memory opening is formed, which includes a volume of an second memory opening that…
Soft data compression for non-volatile memory
Granted: April 4, 2023
Patent Number:
11620050
An encoder of a storage medium receives, at a plurality of latches respectively associated with a plurality of memory cells, soft data corresponding to data subject to a read operation specified by the a storage controller, compresses the soft data, and stores the compressed soft data in a buffer before transmitting the compressed soft data to the storage controller. Upon the buffer being full, the encoder writes uncompressed soft data back to at least a subset of the plurality of…
