Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings
Granted: March 4, 2025
Patent Number:
12245434
A method includes forming an alternating stack of first and second layers, forming a composite hard mask layer over the alternating stack, forming openings in the hard mask, and forming via openings through the alternating stack by performing an anisotropic etch process that transfers a pattern of the openings in the composite hard mask layer through the alternating stack. The compositing hard mask includes a first cladding material layer which has higher etch resistance than upper and…
Three dimensional memory device containing resonant tunneling barrier and high mobility channel and method of making thereof
Granted: March 4, 2025
Patent Number:
12245425
A three-dimensional memory device containing a plurality of levels of memory elements includes a memory film containing a layer stack that includes a resonant tunneling barrier stack, a semiconductor barrier layer, and a memory material layer located between the resonant tunneling barrier stack and the semiconductor barrier layer, a semiconductor channel, and a control gate electrode.
Concurrent multi-bit self-referenced read of programmable resistance memory cells in cross-point array
Granted: February 25, 2025
Patent Number:
12237010
Concurrent access of multiple memory cells in a cross-point memory array is disclosed. In one aspect, a forced current approach is used in which, while a select voltage is applied to a selected bit line, an access current is driven separately through each selected word line to concurrently drive the access current separately through each selected memory cell. Hence, multiple memory cells are concurrently accessed. In some aspects, the memory cells are accessed using a self-referenced…
Securing a data storage device against rogue hosts
Granted: February 25, 2025
Patent Number:
12236112
A method for securing a data storage device (DSD) against rogue behaviour by a host, the method executed by a controller of the DSD and comprising: determining a host type of the host; detecting one or more access activities performed by the host on the DSD; processing the one or more access activities to determine a security threat level of the host, wherein the security threat level is determined by weighting one or more corresponding access activity parameters by one or more impact…
Victim zone selection for zone compaction during garbage collection in zns devices
Granted: February 25, 2025
Patent Number:
12235754
Aspects of a storage device are provided including improved victim zone selection for zone-based GC in ZNS. The storage device includes a NVM having first, second, and third blocks, and a controller. The controller creates a first superblock including the first blocks, a second superblock including the second blocks, and a third superblock including the third blocks. The controller determines whether a quantity of data overwrites associated with a first zone in the first superblock is…
Hold-up capacitor failure handling in data storage devices
Granted: February 18, 2025
Patent Number:
12229416
A data storage device includes a plurality of hold-up capacitors configured to provide back-up power for a non-volatile memory, a controller, and a write cache. The controller is configured to detect one or more failed hold-up capacitors of the plurality of hold-up capacitors; and in response to detecting the one or more failed hold-up capacitors: perform one or more quiesce operations and determine a count of the one or more failed hold-up capacitors. Based on the count of the one or…
Word line layer dependent stress and screen voltage
Granted: February 18, 2025
Patent Number:
12230344
Technology is disclosed for testing a 3D memory structure. The 3D memory structure has blocks with layers of word lines. Each word line is connected to control gates of NAND memory cells. The 3D memory structure may be tested while concurrently applying a set of layer dependent voltages to a corresponding set of word lines. The magnitude of each layer dependent voltage may depend on which layer the word line to which the voltage is applied resides. There may be physical differences…
Data latch programming algorithm for multi-bit-per-cell memory devices
Granted: February 18, 2025
Patent Number:
12230335
A multi-stage method for programming an n-bit memory cell array using a fixed number of data latches is disclosed. The fixed number of data latches may be a reduced number of data latches in sense amplifier and data latch (SADL) peripheral circuitry than is required by existing programming techniques. As such, the die area taken up by the SADL circuitry can be reduced, which in turn, reduces overall chip area. The multi-stage programming method may include utilizing a first data latch to…
Bit line modulation to compensate for cell source variation
Granted: February 18, 2025
Patent Number:
12230333
Systems and methods for bit line modulation to compensate for cell source variation are disclosed. For example, a method for reading data from non-volatile storage comprising determining a first bit line level based on a first programmed data state that is being sensed and determining a second bit line level based on a second programmed data state that is being sensed. As another example, a storage device comprising a first bit line driver configured to generate a first bit line level…
Read collision avoidance in sequential mixed workloads
Granted: February 18, 2025
Patent Number:
12229423
A data storage device processes a mixed workload including a plurality of superblocks to be written to and read from a plurality of memory dies, where each of the plurality of superblocks to be apportioned among the plurality of memory dies. The data storage device writes a first data stripe associated with a first superblock to the plurality of memory dies according to a sequential write pattern, and reads the first data stripe associated with the first superblock from the plurality of…
Hole channel pre-charge to enable large-volume in-place data sanitization of non-volatile memory
Granted: February 18, 2025
Patent Number:
12229415
In NAND memory, data sanitization allows a relatively small unit of data (e.g., less than a block) to be effectively destroyed by increasing threshold voltages of memory cells from their programmed threshold voltage to the highest threshold state. To reduce the amount of disturb on memory cells not selected for data sanitization, prior to applying a program voltage to a target word line, a hole based pre-charge operation is performed. More specifically, for NAND strings having a memory…
Hybrid logical to physical mapping for ZNS based SSDs
Granted: February 18, 2025
Patent Number:
12229403
Aspects of a storage device are provided that handle host commands associated with active and inactive zones using a hybrid L2P mapping system. The storage device includes a NVM, a controller, a first volatile memory and a second volatile memory. The controller allocates, as a superblock, one or more physical blocks respectively in one or more memory dies of the NVM, receives write commands including logical addresses associated with active zones, and stores in an L2P mapping table L2P…
Devices and methods for providing port matching features for USB-C cables and ports
Granted: February 18, 2025
Patent Number:
12229070
Systems and methods are disclosed for providing port matching features for storage devices and cables. In certain embodiments, a data storage device includes a non-volatile memory, a controller configured to process data storage requests, a plurality of ports associated with different protocols, wherein the plurality of ports have the same connector type, and each port includes a port matching feature indicative of a protocol associated with the port, and a plurality of cables associated…
Storage device for storing model checkpoints of recommendation deep-learning models
Granted: February 18, 2025
Patent Number:
12229016
The present disclosure generally relates to utilizing improved DL training models stored in non-volatile memory to optimize data transfer and storage. The proposed system would identify workloads of DNN training and occasionally check the difference rate between successive data transfers (representing successive training iterations of the model). Comparing the difference rate to given thresholds could indicate “recommendation-system” typical use case. In such a case the NAND…
Delayed XOR rebuild with priority in multi-protocol products
Granted: February 18, 2025
Patent Number:
12229008
A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to operate under at least a first device protocol and a second device protocol, where the first and second device protocols have different endurance and protection requirements. When data is programmed to the memory device using the first device protocol, but is read from the memory device using the second device protocol, the differing endurance and protection…
Data storage device holder
Granted: February 18, 2025
Patent Number:
D1062755
Non-volatile memory with concurrent sub-block programming
Granted: February 11, 2025
Patent Number:
12224011
A non-volatile memory system includes a control circuit connected to non-volatile memory cells. The control circuit is configured to concurrently program memory cells connected to different word lines that are in different sub-blocks of different blocks in different planes of a die.
Three-dimensional memory device with doped semiconductor bridge structures and methods for forming the same
Granted: February 11, 2025
Patent Number:
12225720
A vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate, and memory opening fill structures including vertical stacks of memory elements are formed through the vertically alternating sequence. Backside trenches are formed to divide the vertically alternating sequence into a plurality of alternating stacks of insulating layers and sacrificial material layers. Bridge structures are formed within each of the…
Devices and methods for genome sequencing
Granted: February 11, 2025
Patent Number:
12224042
A device includes arrays of Non-Volatile Memory (NVM) cells. Reference sequences representing portions of a genome are stored in respective groups of NVM cells. Exact matching phase substring sequences representing portions of at least one sample read are loaded into groups of NVM cells. One or more groups of NVM cells are identified where the stored reference sequence matches the loaded exact matching phase substring sequence using the arrays at Content Addressable Memories (CAMs).…
Multi-stage data compaction in NAND
Granted: February 11, 2025
Patent Number:
12224014
Technology is disclosed herein for multi-stage data compaction. In a first data compaction stage valid data fragments from source erase block(s) are programmed into a destination erase block at two bits per memory cell. In a second data compaction stage additional valid data from the source erase block(s) is programmed into the destination erase block at two bits per memory cell. In this second stage, the same physical pages of memory cells in the destination erase block may be…
