Three-dimensional memory device including metal silicide source regions and methods for forming the same
Granted: October 25, 2022
Patent Number:
11482539
A memory die includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a memory film, a vertical semiconductor channel, a source region containing a metal silicide material contacting a first end of the vertical semiconductor channel, and a drain region containing a doped semiconductor material contacting a second…
Three-dimensional memory device including multi-bit charge storage elements and methods for forming the same
Granted: October 25, 2022
Patent Number:
11482531
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel, a tunneling dielectric layer, and a vertical stack of memory elements located at levels of the electrically conductive layers between a respective vertically neighboring pair of the insulating layers.…
ECC in integrated memory assembly
Granted: October 25, 2022
Patent Number:
11482296
Technology for error correcting data stored in memory dies is disclosed. Codewords, which may contain data bits and parity bits, are stored on a memory die. The memory die is bonded to a control die through bond pads that allow communication between the memory die and the control die. The codewords are decoded at the control die based on the parity bits. If the control die successfully decodes a codeword, the control die may send the data bits but not the parity bits to a memory…
Application based verify level offsets for non-volatile memory
Granted: October 25, 2022
Patent Number:
11482289
A memory apparatus and method of operation are provided. The apparatus includes a plurality of memory cells. Each of the plurality of memory cells is connected to one of a plurality of word lines and is arranged in one of a plurality of blocks. Each of the plurality of memory cells is configured to retain a threshold voltage corresponding to one of a plurality of data states. A control circuit is coupled to the plurality of word lines and is configured to detect at least one use…
Per pin Vref for data receivers in non-volatile memory system
Granted: October 25, 2022
Patent Number:
11482262
Technology is disclosed herein for per pin internal reference voltage generation for data receivers in non-volatile memory systems. A receiving circuit may have an on-die voltage generator that has inputs to receive a separate voltage magnitude select signal for each data receiver on the receiving circuit. The on-die voltage generator provides a separate reference voltage for each data receiver. This allows the reference voltage for each data receiver to be calibrated separately. A…
Non-volatile memory with memory array between circuits
Granted: October 25, 2022
Patent Number:
11481154
An integrated memory assembly comprises a memory die and a control die bonded to the memory die. The memory die comprises a three dimensional non-volatile memory structure and a first plurality of sense amplifiers. The first plurality of sense amplifiers are connected to the memory structure and are positioned on a substrate of the memory die between the memory structure and the substrate such that the memory structure is directly above the first plurality of sense amplifiers. The…
Modified verify in a memory device
Granted: October 18, 2022
Patent Number:
11475967
The non-volatile memory includes a control circuitry that is communicatively coupled to an array of memory cells that are arranged word lines. The control circuitry is configured to program the memory cells using a multi-pass programming operation which includes a first pass and a second pass. The first pass programs the memory cells to a first number of data states, and the second pass programs the memory cells to a greater second number of data states. For at least one word line,…
Spark gap electrostatic discharge (ESD) protection for memory cards
Granted: October 18, 2022
Patent Number:
11477881
To protect memory cards, such as SD type cards, and similar devices from Electrostatic Discharge (ESD), the input pads of the device include points along their edges that are aligned with correspond points on a conductive frame structure mounted adjacent the input pad to form a spark gap. The input pads are connected to a memory controller or other ASIC over signal lines that include a diode located between the input pad and the ASIC and a resistance located between the input pad and the…
Spin-transfer torque MRAM with a negative magnetic anisotropy assist layer and methods of operating the same
Granted: October 18, 2022
Patent Number:
11476409
A MRAM device includes a magnetic tunnel junction containing a reference layer having a fixed magnetization direction, a free layer, and a nonmagnetic tunnel barrier layer located between the reference layer and the free layer, a negative-magnetic-anisotropy assist layer having negative magnetic anisotropy that provides an in-plane magnetization within a plane that is perpendicular to the fixed magnetization direction, and a first nonmagnetic spacer layer located between the free layer…
Three-dimensional memory device with a graphene channel and methods of making the same
Granted: October 18, 2022
Patent Number:
11476272
Memory stack structures extending through an alternating stack of insulating layers and electrically conductive layers is formed over a substrate. Each memory stack structure includes a memory film and a vertical semiconductor channel. A sacrificial polycrystalline metal layer may be formed on each memory film, and a carbon precursor may be decomposed on a physically exposed surface of the sacrificial polycrystalline metal layer to generate adsorbed carbon atoms. A subset of the adsorbed…
Nonvolatile memory with efficient look-ahead read
Granted: October 18, 2022
Patent Number:
11475961
An apparatus includes one or more control circuits configured to connect to a plurality of non-volatile memory cells through a plurality of word lines. The one or more control circuits are configured to, for each target word line of a plurality of target word lines to be read, select either a first neighboring word line or a second neighboring word line as a selected neighboring word line according to whether non-volatile memory cells of the first neighboring word line are in an erased…
Reduced program time for memory cells using negative bit line voltage for enhanced step up of program bias
Granted: October 18, 2022
Patent Number:
11475959
Apparatuses and techniques are described for reducing the program time for a set of memory cells by using an enhanced step up of a program bias. A program operation includes a first pass in which memory cells are programmed to intermediate states and a second program pass in which the memory cells are programmed from an erased state and the intermediate states to final states. In the first program pass, program time can be reduced by applying an enhanced program bias step up to memory…
Negative bit line biasing during quick pass write programming
Granted: October 18, 2022
Patent Number:
11475958
A method of operating a memory system includes a first programming loop, which includes applying a first programming voltage to a control gate of a selected word line and applying a first bitline voltage to a bitline coupled to a first memory cell that is being programmed to a first data state and to a different bitline coupled to a second memory cell that is being programmed to a second data state. In a second programming loop, a second bitline voltage is applied to the bitline coupled…
Optimized programming with a single bit per memory cell and multiple bits per memory cell
Granted: October 18, 2022
Patent Number:
11475957
Apparatuses and techniques are described for optimizing programming in a memory device in which memory cells can be programmed using single bit per cell programming and multiple bits per cell programming. In one aspect, a single bit per cell program operation is performed which reduces damage to the memory cells as well as reducing program time. The program operation can omit a pre-charge phase and a verify phase of an initial program loop of a program operation. Instead, a program phase…
Method and apparatus for depositing a multi-sector film on backside of a semiconductor wafer
Granted: October 18, 2022
Patent Number:
11473199
A patterned backside stress compensation film having different stress in different sectors is formed on a backside of a substrate to reduce combination warpage of the substrate. The film can be formed by employing a radio frequency electrode assembly including plurality of conductive plates that are biased with different RF power and cause local variations in the plasma employed to deposit the backside film. Alternatively, the film may be deposited with uniform stress, and some of its…
Memory device using a multilayer ferroelectric stack and method of forming the same
Granted: October 11, 2022
Patent Number:
11469251
A memory device includes a semiconductor channel, a gate electrode, and a stack located between the semiconductor channel and the gate electrode. The stack includes, from one side to another, a first ferroelectric material portion, a second ferroelectric material portion, and a gate dielectric portion that contacts the semiconductor channel.
Three-dimensional memory device including discrete charge storage elements and methods of forming the same
Granted: October 11, 2022
Patent Number:
11469241
An alternating stack of insulating layers and spacer material layers can be formed over a substrate. The spacer material layers may be formed as, or may be subsequently replaced with, electrically conductive layers. A memory opening can be formed through the alternating stack, and annular lateral recesses are formed at levels of the insulating layers. Metal portions are formed in the annular lateral recesses, and a semiconductor material layer is deposited over the metal portions.…
Memory programming with selectively skipped bitscans and fewer verify pulses for performance improvement
Granted: October 11, 2022
Patent Number:
11468950
An apparatus that includes a word line with a plurality of memory cells that are able to be programmed to a plurality of data states is provided. The apparatus further includes a programming circuit. The programming circuit is configured to program the memory cells and count the number of verify pulses at a first verify voltage level that are performed during programming of the memory cells to a first programmed data state to determine a verify count. During programming to a second data…
Managed fetching and execution of commands from submission queues
Granted: October 11, 2022
Patent Number:
11467769
The disclosure relates in some aspects to managing the fetching and execution of commands stored in submission queues. For example, execution of a command may be blocked at a data storage apparatus due to an internal blocking condition (e.g., a large number of commands of a particular type are pending for execution at the data storage device). As another example, execution of a command may be blocked at a data storage apparatus due to an external blocking condition (e.g., a host device…
Multi-level program pulse for programming single level memory cells to reduce damage
Granted: September 27, 2022
Patent Number:
11456042
Apparatuses and techniques are described for reducing damage to memory cells during single bit per cell programming. An initial program pulse in a single bit per cell program operation has a lower, first program level followed by a higher, second program level. As a result of the lower, first program level, the electric field across the memory cells is reduced. The step up time from the first program level to the second program level can be reduced by concurrently stepping up pass…
