METHODS FOR MANUFACTURING INTEGRATED CIRCUIT DEVICES HAVING FEATURES WITH REDUCED EDGE CURVATURE
Granted: February 11, 2016
Application Number:
20160043174
A structure, such as an integrated circuit device, is described that includes a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in etching the line. Techniques are described for processing a line of crystalline phase material which has already been etched using the mask element, in a manner which straightens an etched sidewall surface of the line. The straightened sidewall…
PATH-BASED FLOORPLAN ANALYSIS
Granted: February 11, 2016
Application Number:
20160042115
Systems and techniques for computing a timing effort metric are described. According to one definition, the computed timing effort metric indicates a level of difficulty of fixing a timing violation associated with a timing path between two circuit objects in a circuit design layout.
OPTIMIZING CONSTRAINT SOLVING BY REWRITING AT LEAST ONE BIT-SLICE CONSTRAINT
Granted: February 4, 2016
Application Number:
20160034624
Methods and apparatuses are described for assigning random values to a set of random variables so that the assigned random values satisfy a set of constraints. A constraint solver can receive a set of constraints that is expected to cause performance problems when the system assigns random values to the set of random variables in a manner that satisfies the set of constraints. For example, modulo constraints and bit-slice constraints can cause the system to perform excessive backtracking…
LATCH-UP SUPPRESSION AND SUBSTRATE NOISE COUPLING REDUCTION THROUGH A SUBSTRATE BACK-TIE FOR 3D INTEGRATED CIRCUITS
Granted: February 4, 2016
Application Number:
20160034620
Roughly described, an integrated circuit device has a conductor extending entirely through the substrate, connected on one end to the substrate topside surface and on the other end to the substrate backside surface. In various embodiments the conductor is insulated from all RDL conductors on the backside of the substrate, and/or is insulated from all conductors and device features on any below-adjacent chip in a 3D integrated circuit structure. Methods of fabrication are also described.
EQUIVALENCE CHECKING BETWEEN TWO OR MORE CIRCUIT DESIGNS THAT INCLUDE SQUARE ROOT CIRCUITS
Granted: January 14, 2016
Application Number:
20160012177
Methods and apparatuses are described for proving equivalence between two or more circuit designs that include one or more division circuits and/or one or more square-root circuits. Some embodiments analyze the circuit designs to determine an input relationship between the inputs of two division (or square-root) circuits. Next, the embodiments determine an output relationship between the outputs of two division (or square-root) circuits based on the input relationship. The embodiments…
INCREMENTAL SLACK MARGIN PROPAGATION
Granted: January 14, 2016
Application Number:
20160012166
Techniques and systems are described for improving the efficiency of timing calculations in numerical sequential cell sizing and for improving the efficiency of incremental slack margin propagation. Some embodiments cache timing-related information associated with a source driver that drives an input of a sequential cell that is being sized, and/or timing-related information for each output of the sequential cell that is being sized. The cached timing-related information for the source…
GROUND OFFSET MONITOR AND COMPENSATOR
Granted: January 14, 2016
Application Number:
20160011234
Methods and systems are described for monitoring and compensating an offset between a reference voltage used in a first device and a corresponding reference voltage used in a second device. The first device can include offset circuitry. The offset circuitry receives two voltage signals. The first voltage signal is equal to a first voltage value that is used as a reference voltage in the first device. The second voltage signal can be a time-varying voltage signal that has a known…
NANOWIRE OR 2D MATERIAL STRIPS INTERCONNECTS IN AN INTEGRATED CIRCUIT CELL
Granted: December 24, 2015
Application Number:
20150370949
An integrated circuit design tool includes a cell library. The cell library includes entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language. At least one entry in the cell library can comprise a specification of physical structures and timing parameters of a circuit including a first transistor, a second transistor, and an interconnect connecting a terminal of the first transistor to a terminal of the…
CELLS HAVING TRANSISTORS AND INTERCONNECTS INCLUDING NANOWIRES OR 2D MATERIAL STRIPS
Granted: December 24, 2015
Application Number:
20150370951
An integrated circuit design tool includes a cell library. The cell library includes entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language. At least one entry in the cell library can comprise a specification of physical structures and timing parameters of a plurality of transistors and an interconnect; wherein a transistor in the plurality has a channel comprising one or more nanowires or 2D material…
ARRAY WITH INTERCELL CONDUCTORS INCLUDING NANOWIRES OR 2D MATERIAL STRIPS
Granted: December 24, 2015
Application Number:
20150370950
An integrated circuit design tool includes a cell library. The cell library includes entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language. At least one entry in the cell library can comprise a specification of physical structures and timing parameters of an array of circuit cells, the circuit cells including one or more transistors and a cell interconnect terminal; and a conductor configured to…
MEMORY CELLS HAVING TRANSISTORS WITH DIFFERENT NUMBERS OF NANOWIRES OR 2D MATERIAL STRIPS
Granted: December 24, 2015
Application Number:
20150370948
An integrated circuit design tool includes a cell library. The cell library includes entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language. At least one entry in the cell library can comprise a specification of physical structures and timing parameters of a memory cell including a plurality of transistors, at least some of the transistors in the plurality having channels comprising respective sets of…
DESIGN TOOLS FOR INTEGRATED CIRCUIT COMPONENTS INCLUDING NANOWIRES AND 2D MATERIAL STRIPS
Granted: December 24, 2015
Application Number:
20150370947
An integrated circuit design tool includes a cell library. An entry in the cell library comprises a specification of the cell including a first transistor and a second transistor. The first transistor can include a first set of nanowires or 2D material strips arranged in parallel to form a channel structure, and a gate conductor disposed across the first set of nanowires or 2D material strips. The second transistor can include a second set of nanowires or 2D material strips arranged in…
EVALUATION OF THERMAL INSTABILITY STRESS TESTING
Granted: December 24, 2015
Application Number:
20150369855
A circuit is powered through a transistor whose thermal instability behavior is to be evaluated in a stress test. The transistor is stressed during a stress phase of the stress test with a sensor circuit powered off and the Vds of the transistor is zero. The sensor circuit is powered on through the transistor during an evaluate phase of the stress test.
RESOLUTION ENHANCEMENT TECHNIQUES BASED ON HOLOGRAPHIC IMAGING TECHNOLOGY
Granted: November 26, 2015
Application Number:
20150339802
Systems and techniques for performing resolution enhancement on target patterns based on holographic imaging technique (HIT) are described. During operation, an electronic design automation (EDA) tool can compute an in-line hologram of the target patterns based on parameters associated with a photolithography process that is used in a semiconductor manufacturing process, wherein the semiconductor manufacturing process is to be used for printing the target patterns on a semiconductor…
FLOATING METAL FILL CAPACITANCE CALCULATION
Granted: November 12, 2015
Application Number:
20150324511
A design layout is obtained that includes floating fill shapes and signal shapes. Capacitance of the signal shapes is calculated. A simple model is used to calculate a first subset of fill shapes which contribute capacitance to the signal shapes. A capacitance model selected to meet an acceptable error level using minimum computational requirements is then selected from a set of capacitance models. The selected capacitance model is then used to extract the capacitance contribution from…
Multi-Bit Standard Cells For Consolidating Transistors With Selective Sourcing
Granted: November 5, 2015
Application Number:
20150318845
A method for designing a standard cell, e.g. a multi-bit flip-flop, can include identifying a first set of transistors. This first set functions to source power or ground to circuits of the standard cell. A second set of transistors can be determined and correlated. This second set forms at least part of the first set of transistors. Each correlated group in the second set of transistors receives identical signals, e.g. scan enable, reset, and/or set signals, and provides a same…
3D TCAD SIMULATION
Granted: November 5, 2015
Application Number:
20150317420
A first representation of an integrated circuit undergoing processing is transformed into a second representation. The second representation including additional dopants relative to the first representation. The transformation generates a three-dimensional dopant distribution from adding a first dopant under a first set of process conditions with a mask, by combining the two-dimensional lateral profile of the dopant with the one-dimensional depth profile of the dopant. The…
FINFET CELL ARCHITECTURE WITH POWER TRACES
Granted: October 22, 2015
Application Number:
20150303196
A finFET block architecture suitable for use of a standard cell library, is based on an arrangement including a first set of semiconductor fins in a first region of the substrate having a first conductivity type, and a second set of semiconductor fins in a second region of the substrate, the second region having a second conductivity type. A patterned gate conductor layer including gate traces in the first and second regions, arranged over channel regions of the first and second sets of…
MASK3D MODEL ACCURACY ENHANCEMENT FOR SMALL FEATURE COUPLING EFFECT
Granted: October 22, 2015
Application Number:
20150302132
A method and apparatus of a novel full chip edge-based mask three-dimensional (3D) model for performing photolithography simulation with consideration for edge coupling effect is described. The method receives a mask design layout in order to perform mask topography effect modeling. The method generates scaling parameters for edge coupling effects. Each scaling parameter has an associated combination of feature width and space. The sum of feature width and space associated with at least…
SYSTEMS AND METHODS FOR INCREASING DEBUGGING VISIBILITY OF PROTOTYPING SYSTEMS
Granted: October 15, 2015
Application Number:
20150294055
User's register transfer level (RTL) design is analyzed and instrumented so that signals of interest are preserved and can be located in the netlist after synthesis. Then, the user's original flow of RTL synthesis and design partition is performed. The output is analyzed to locate the signals of interest. Latches are selectively inserted to the netlist to ensure that signal values can be accessed at runtime. After that, a place and route (P&R) process is performed, and the outputs…
