Design Tools For Converting a FinFet Circuit into a Circuit Including Nanowires and 2D Material Strips
Granted: November 17, 2016
Application Number:
20160335387
An integrated circuit design tool includes a cell library. An entry in the cell library comprises a specification of the cell including a first transistor and a second transistor. The first transistor can include a first set of nanowires or 2D material strips arranged in parallel to form a channel structure, and a gate conductor disposed across the first set of nanowires or 2D material strips. The second transistor can include a second set of nanowires or 2D material strips arranged in…
MULTI-SCALE SIMULATION INCLUDING FIRST PRINCIPLES BAND STRUCTURE EXTRACTION
Granted: November 17, 2016
Application Number:
20160335381
Electronic design automation modules include a first tool and a second tool. The first tool includes ab initio simulation procedures configured to use input parameters to produce information about a band structure of a simulated material on a first simulation scale specified at least in part by the input parameters. The second tool includes a simulation procedure configured to used information about the band structure of the simulated material produced by the first tool to extract…
METHOD AND APPARATUS FOR AUTOMATIC RELATIVE PLACEMENT GENERATION FOR CLOCK TREES
Granted: November 17, 2016
Application Number:
20160335376
Methods and apparatuses are disclosed for automatic relative placement of part of a clock tree in the course of generating a placed, routed, and optimized circuit design.
CELLS HAVING TRANSISTORS AND INTERCONNECTS INCLUDING NANOWIRES OR 2D MATERIAL STRIPS
Granted: November 10, 2016
Application Number:
20160329313
An integrated circuit design tool includes a cell library. The cell library includes entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language. At least one entry in the cell library can comprise a specification of physical structures and timing parameters of a plurality of transistors and an interconnect; wherein a transistor in the plurality has a channel comprising one or more nanowires or 2D material…
SYSTEM AND METHOD FOR REACTIVE INITIALIZATION BASED FORMAL VERIFICATION OF ELECTRONIC LOGIC DESIGN
Granted: October 13, 2016
Application Number:
20160300009
A system and method use reactive initialization to facilitate formal verification of an electronic logic design. The system verifies that a part of the logic design correctly transitions through a sequence of states by automatically assigning an initial state value. The system interacts with a correction-unit to provide meaningful feedback of verification failures, making it possible for the correction-unit to correct the failures or add new constraints that allow the verification to…
SYSTEM AND METHOD FOR POWER VERIFICATION USING EFFICIENT MERGING OF POWER STATE TABLES
Granted: October 6, 2016
Application Number:
20160292346
A power verification system requires a combination of design and its power intent. A power intent (PI) input specifies the power architecture of a design through specification of power/voltage domains, their corresponding power supplies and a collection of power management devices. Power state tables (PSTs) specified in PI capture the legal combinations of power states (voltage values) for the various sets of supply nets or supply ports of a design. A power verification system requires…
CLOCK-DOMAIN-CROSSING SPECIFIC DESIGN MUTATIONS TO MODEL SILICON BEHAVIOR AND MEASURE VERIFICATION ROBUSTNESS
Granted: October 6, 2016
Application Number:
20160292331
Methods and apparatuses related to clock-domain-crossing (CDC) specific design mutations to model silicon behavior and measure verification robustness are described. CDC signal paths can be identified in a circuit design. Next, synchronization circuitry associated with the CDC signal paths can be identified. Design mutations can be added to the identified synchronization circuitry. The design mutations can then be used during functional verification to measure verification robustness of…
NANOWIRE OR 2D MATERIAL STRIPS INTERCONNECTS IN AN INTEGRATED CIRCUIT CELL
Granted: September 29, 2016
Application Number:
20160284704
An integrated circuit design tool includes a cell library. The cell library includes entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language. At least one entry in the cell library can comprise a specification of physical structures and timing parameters of a circuit including a first transistor, a second transistor, and an interconnect connecting a terminal of the first transistor to a terminal of the…
SCALABLE CHIP PLACEMENT
Granted: September 29, 2016
Application Number:
20160283632
Some embodiments can receive a netlist for the circuit design, wherein the netlist is divided into a set of blocks and a top-level netlist. Next, the embodiments can create (1) a top-level netlist abstraction based on the top-level netlist, and (2) for each block in the set of blocks, create a block abstraction based on a portion of the netlist that is in the block and create virtual pin cells in the block, wherein each virtual pin cell corresponds to a connection that crosses a boundary…
TRANSPARENT EDITING OF PHYSICAL DATA IN HIERARCHICAL INTEGRATED CIRCUIT DESIGN
Granted: September 22, 2016
Application Number:
20160275228
Systems and techniques are described for transparently editing physical data in hierarchical IC designs. Some embodiments allow a user to access objects at any level of the physical hierarchy and to specify a particular editing operation (move, rotate, delete, cut, split, etc.) relative to the top-level block. The embodiments can automatically transform and apply the editing operations in the context of the block where the edited object resides. Systems and techniques for automatic…
SYSTEM AND METHOD FOR NETLIST CLOCK DOMAIN CROSSING VERIFICATION
Granted: September 8, 2016
Application Number:
20160259879
A system and method for netlist clock domain crossing verification leverages RTL clock domain crossing (CDC) verification data and results. The netlist clock domain crossing verification system (NCDC) migrates RTL-level constraints and waivers to the netlist design so that the user does not have to re-enter them. The NCDC checks the netlist and generates a report that compares RTL-level CDC checking results to the netlist-level CDC checking results to make it easy to see new issues. The…
FIRST PRINCIPLES DESIGN AUTOMATION TOOL
Granted: August 11, 2016
Application Number:
20160232264
An electronic design automation tool includes an application program interface API. The API includes a set of parameters and procedures supporting atomistic scale modeling of electronic materials. The procedures include a procedure to execute first principles calculations, a procedure to process results from the first principles calculations to extract device scale parameters from the results, and a procedure to determine whether the device scale parameters extracted from the results lie…
METHOD AND SYSTEM FOR SELECTING STIMULATION SIGNALS FOR POWER ESTIMATION
Granted: July 28, 2016
Application Number:
20160217239
A power estimation signal selection tool identifies the signals of an IC design that should be captured in waveform data and activity formats during simulation or emulation. The power estimation signal tool reduces the volume of simulation data produced by a simulator. Signals of at least one specified type are captured in a simulated waveform data (SWD) format. Alternatively, only signals affecting “when” power conditions and abstract RTL expressions are captured in the SWD format,…
PARAMETER EXTRACTION OF DFT
Granted: July 28, 2016
Application Number:
20160217234
Electronic design automation to simulate the behavior of structures and materials at multiple simulation scales with different simulators.
Mapping Intermediate Material Properties To Target Properties To Screen Materials
Granted: June 9, 2016
Application Number:
20160162625
A system for evaluating candidate materials for fabrication of integrated circuits includes a data processor coupled to a memory. Roughly described, the data processor is configured to: calculate and write to a first database, for each of a plurality of candidate materials, values for each property in a set of intermediate properties; calculate and write to a second database, values for a selected target property for various combinations of values for the intermediate properties and…
FINFET WITH HETEROJUNCTION AND IMPROVED CHANNEL CONTROL
Granted: March 24, 2016
Application Number:
20160087099
Roughly described, a computer program product describes a transistor with a fin, a fin support, a gate, and a gate dielectric. The fin includes a first crystalline semiconductor material which includes a channel region of the transistor between a source region of the first transistor and a drain region of the transistor. The fin is on a fin support. The fin support includes a second crystalline semiconductor material different from the first crystalline semiconductor material. The first…
EXPONENTIALLY FITTED APPROXIMATION FOR ANISOTROPIC SEMICONDUCTOR EQUATIONS
Granted: March 10, 2016
Application Number:
20160070833
Roughly described, a method for determining characteristics of a body by simulation, useful in analyzing semiconductor devices, includes imposing a Delaunay mesh on a simulated body to be modeled, determining a system of node equations describing generation and flux of a set of at least a first physical quantity at each node in the mesh, and numerically solving the system of node equations to identify the physical quantities in the set at each node in the mesh, where the flux of the…
ARRAYS WITH COMPACT SERIES CONNECTION FOR VERTICAL NANOWIRES REALIZATIONS
Granted: March 3, 2016
Application Number:
20160063163
An integrated circuit design tool includes a functional cell library. An entry in the cell library comprises a specification of the cell. Entries in the cell library including specifications of particular cells in a computer executable language. At least one entry in the cell library comprising a specification of a cell including a plurality of transistors and an interconnect. At least two transistors in the plurality are in series via at least the interconnect. The transistors and the…
SYSTEM AND METHOD USING PASS/FAIL TEST RESULTS TO PRIORITIZE ELECTRONIC DESIGN VERIFICATION REVIEW
Granted: March 3, 2016
Application Number:
20160063162
A system and method are provided that use pass/fail test results to prioritize electronic design verification review issues. It may prioritize either generated properties or code coverage items or both. Thus issues, whether generated properties or code coverage items, that have never been violated in any passing or failing test may be given highest priority for review, while those that have been violated in a failing test but are always valid in passing tests may be given lower priority.…
FINFET CELL ARCHITECTURE WITH POWER TRACES
Granted: February 11, 2016
Application Number:
20160043083
A finFET block architecture suitable for use of a standard cell library, is based on an arrangement including a first set of semiconductor fins in a first region of the substrate having a first conductivity type, and a second set of semiconductor fins in a second region of the substrate, the second region having a second conductivity type. A patterned gate conductor layer including gate traces in the first and second regions, arranged over channel regions of the first and second sets of…
