INTEGRATED CIRCUIT DEVICES HAVING FEATURES WITH REDUCED EDGE CURVATURE AND METHODS FOR MANUFACTURING THE SAME
Granted: October 15, 2015
Application Number:
20150295021
A structure such as an integrated circuit device is described having a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in manufacturing the line of material.
MOST ACTIVATED MEMORY PORTION HANDLING
Granted: October 1, 2015
Application Number:
20150279441
Activation of portions of a memory is tracked to allow an affected portion of the memory to be refreshed before it is corrupted by multiple activations. An address for the accessed portion of memory, called the aggressor row, is compared to addresses stored in a content addressable memory (CAM). If the address is not already stored in the CAM, it is stored, casting out another address if necessary, and a count based on an Others value is stored in the CAM with the address. If the address…
GOAL-BASED CELL PARTITIONING IN THE PRESENCE OF OBSTACLES
Granted: September 24, 2015
Application Number:
20150269301
Systems and techniques are provided to correctly handle obstacles during cell partitioning, thereby preventing electronic design automation (EDA) tools from being subject to performance penalties during subsequent operations that are performed by the EDA tools on the cell partitions.
NETWORK FLOW BASED FRAMEWORK FOR CLOCK TREE OPTIMIZATION
Granted: September 24, 2015
Application Number:
20150269298
Systems and techniques for clock tree optimization are described. An electronic design automation (EDA) tool can receive a graph that represents a circuit design, wherein a set of trees in the graph can correspond to a set of clock trees in the circuit design. For each tree in the set of trees, a set of leaf node pairs can be determined. Next, for each leaf node pair, a flow can be created in the graph between the two leaf nodes in the leaf node pair. Aggregate flows can be determined…
FINFET CELL ARCHITECTURE WITH INSULATOR STRUCTURE
Granted: September 17, 2015
Application Number:
20150261894
A finFET block architecture includes a first set of semiconductor fins having a first conductivity type, and a second set of semiconductor fins having a second conductivity type. An inter-block insulator is placed between outer fins of the first and second sets. A patterned gate conductor layer includes a first plurality of gate traces extending across the set of fins in the first block without crossing the inter-block insulator, and a second plurality of gate traces extending across the…
HIGH VOLTAGE SWITCH WITH TWO OR MORE OUTPUTS
Granted: September 10, 2015
Application Number:
20150256171
Embodiments relate to a single multi-output high-voltage (HV) switch configured to pass multiple HV signals in semiconductor integrated circuits, such as a memory device. By utilizing a single HV switch that shares multiple components, area is reduced and fewer numbers of transistor devices are used to reduce cost. The shared components are selected such that the HV switch configuration provides functionality similar to traditional multiple HV switch configurations. Specifically, common…
ASSERTION EXTRACTION FROM DESIGN AND ITS SIGNAL TRACES
Granted: August 27, 2015
Application Number:
20150242541
Groups of signals in an electronic design for which interesting assertions, such as assert, assume and cover properties, can be generated are identified. A sliding temporal window of fixed depth is used to sample unique present and past value combinations of signals in the signals groups generated by one or more simulations or emulations. The values of signals in the signal groups are organized into truth tables. Minimal functional relations are extracted from the truth tables, using…
IDENTIFYING LAYOUT PATTERN CANDIDATES
Granted: August 13, 2015
Application Number:
20150227670
A method, system or computer usable program product for automatically identifying layout pattern candidates in selected regions for use in analyzing semiconductor device performance issues including identifying a set of target regions and a set of reference regions from a design layout; utilizing a processor to generate a reference baseline of layout patterns from the set of reference regions; utilizing the processor to compare a frequency profile of layout patterns in the set of target…
PLACEMENT OF SINGLE-BIT AND MULTI-BIT FLIP-FLOPS
Granted: August 13, 2015
Application Number:
20150227646
Technology is disclosed for placement of single-bit flip-flops and multi-bit flip-flops. Single-bit flip-flops with replaced with multi-bit flip-flops and/or relative placement groups of single-bit flip-flops.
Protection Scheme for Embedded Code
Granted: August 6, 2015
Application Number:
20150220458
A code protection scheme for controlling access to a memory region in an integrated circuit includes a processor with an instruction pipeline that includes multiple processing stages. A first processing stage receives one or more instructions. A second processing stage receives address information identifying a protected memory region of the memory from the first processing stage and protection information for an identified protected memory region. The protection information indicates a…
INVARIANT SHARING TO SPEED UP FORMAL VERIFICATION
Granted: July 30, 2015
Application Number:
20150213167
Methods and apparatuses are described for sharing inductive invariants while performing formal verification of a circuit design. Specifically, some embodiments assume at least an inductive invariant for a property to be true while proving another property. According to one definition, an inductive invariant of a property is an inductive assertion such that all states that satisfy the inductive assertion also satisfy the property. According to one definition, an inductive assertion…
METHOD AND APPARATUS FOR AUTOMATIC RELATIVE PLACEMENT GENERATION FOR CLOCK TREES
Granted: July 30, 2015
Application Number:
20150213159
Methods and apparatuses are disclosed for automatic relative placement of part of a clock tree in the course of generating a placed, routed, and optimized circuit design.
PLACING TRANSISTORS IN PROXIMITY TO THROUGH-SILICON VIAS
Granted: July 23, 2015
Application Number:
20150205904
Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the…
N-CHANNEL AND P-CHANNEL END-TO-END FINFET CELL ARCHITECTURE WITH RELAXED GATE PITCH
Granted: July 9, 2015
Application Number:
20150194429
A finFET block architecture uses end-to-end finFET blocks in which the fin lengths are at least twice the contact pitch, whereby there is enough space for interlayer connectors to be placed on the proximal end and the distal end of a given semiconductor fin, and on the gate element on the given semiconductor fin. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. Interlayer…
Controlling Timing of Negative Charge Injection to Generate Reliable Negative Bitline Voltage
Granted: June 18, 2015
Application Number:
20150170721
Embodiments relate to preventing or mitigating excessive drop in the negative voltage level of a bitline of memory bitcells by controlling the delay of a trigger signal for initiating injection of negative charge into the bitline. A write assist circuit causes negative charge to drop gradually in response to receiving a data input indicating a negative value of the bitline. When supply voltage is high, the timed delay of trigger signal is reduced, thereby causing negative charge to be…
METHOD AND APPARATUS FOR FLOATING OR APPLYING VOLTAGE TO A WELL OF AN INTEGRATED CIRCUIT
Granted: June 11, 2015
Application Number:
20150162320
In one well bias arrangement, no well bias voltage is applied to the n-well, and no well bias voltage is applied to the p-well. Because no external well bias voltage is applied, the n-well and the p-well are floating, even during operation of the devices in the n-well and the p-well. In another well bias arrangement, the lowest available voltage is not applied to the p-well, such as a ground voltage, or the voltage applied to the n+-doped source region of the n-type transistor in the…
INTEGRATED MASK-AWARE LITHOGRAPHY MODELING TO SUPPORT OFF-AXIS ILLUMINATION AND MULTI-TONE MASKS
Granted: June 11, 2015
Application Number:
20150161302
A method and apparatus of a novel modeling scheme for performing optical lithography simulation for a multi-tone mask with a plurality of mask tones is described. The method generates a transmission function matrix based on a setting of the multi-tone mask. The method applies the transmission function matrix to transform a formula for calculating light intensity from Abbe's form to Hopkins' form while maintaining the accuracy of Abbe's form. The method then computes the light intensity…
METHODS FOR FABRICATING HIGH-DENSITY INTEGRATED CIRCUIT DEVICES
Granted: May 21, 2015
Application Number:
20150143306
An integrated circuit device having a plurality of lines is described in which the widths of the lines, and the spacing between adjacent lines, vary within a small range which is independent of variations due to photolithographic processes, or other patterning processes, involved in manufacturing the device. A sequential sidewall spacer formation process is described for forming an etch mask for the lines, which results in first and second sets of sidewall spacers arranged in an…
FINFET CELL ARCHITECTURE WITH POWER TRACES
Granted: May 21, 2015
Application Number:
20150137256
A finFET block architecture suitable for use of a standard cell library, is based on an arrangement including a first set of semiconductor fins in a first region of the substrate having a first conductivity type, and a second set of semiconductor fins in a second region of the substrate, the second region having a second conductivity type. A patterned gate conductor layer including gate traces in the first and second regions, arranged over channel regions of the first and second sets of…
SRAM LAYOUTS
Granted: April 23, 2015
Application Number:
20150113492
Roughly described, the cell layout in an SRAM array is re-arranged such that the gate electrodes for transistors for which flexibility to use one channel length is desired, are formed along a different track from those for transistors for which flexibility to use a different channel length is desired. Not only does such a re-arrangement permit optimization of device ratios, but also in certain implementations can also reduce, rather than increase, cell area. Specific example layouts are…
