DISPLAY WITH RETROREFLECTIVE ELEMENTS
Granted: April 16, 2015
Application Number:
20150103392
In one embodiment, an apparatus includes a retroreflector pixel that includes multiple retroreflector sub-pixels. Each retroreflector sub-pixel includes a reflective surface configured to reflect incident light. Each retroreflector sub-pixel also includes a filter element configured to filter out from the incident light an electrically-controllable amount of light over a particular wavelength range. The filter element may utilize an electrophoretic technique based on charged particles,…
ADAPTIVE PARALLELIZATION FOR MULTI-SCALE SIMULATION
Granted: March 26, 2015
Application Number:
20150089511
Roughly described, a task control system for managing multi-scale simulations receives a case/task list which identifies cases to be evaluated, at least one task for each of the cases, and dependencies among the tasks. A module allocates available processor cores to at least some of the tasks, constrained by the dependencies, and initiates execution of the tasks on allocated cores. A module, in response to completion of a particular one of the tasks, determines whether or not the result…
CHARACTERIZING TARGET MATERIAL PROPERTIES BASED ON PROPERTIES OF SIMILAR MATERIALS
Granted: March 26, 2015
Application Number:
20150088803
Roughly described, a technique for approximating a target property of a target material is provided. For each material in a plurality of anchor materials, a correspondence is provided between the value for a predetermined index property of the material and a value for the target property of the material, the values of all the index properties being different. A predictor function is identified in dependence upon the correspondence. A computer system determines a value for the target…
ITERATIVE SIMULATION WITH DFT AND NON-DFT
Granted: March 26, 2015
Application Number:
20150088481
Electronic design automation modules for simulate the behavior of structures and materials at multiple simulation scales with different simulation modules.
SIMULATION SCALING WITH DFT AND NON-DFT
Granted: March 26, 2015
Application Number:
20150088473
Electronic design automation modules for simulate the behavior of structures and materials at multiple simulation scales with different simulation modules.
NVM DEVICE USING FN TUNNELING WITH PARALLEL POWERED SOURCE AND DRAIN
Granted: March 26, 2015
Application Number:
20150085585
A nonvolatile memory (“NVM”) bitcell includes a capacitor, a transistor, and a tunneling device. The capacitor, transistor, and tunneling device are each electrically coupled to different active regions and metal contacts. The three devices are coupled by a floating gate that traverses the three active regions. The tunneling device is used to program and erase the device, allowing for faster page erasure, and thus allows for rapid testing and verification of functionality. The…
INPUT TRIGGER INDEPENDENT LOW LEAKAGE MEMORY CIRCUIT
Granted: March 26, 2015
Application Number:
20150085566
Wordline-driver biasing and column-based source-biasing circuitry facilitate reduced current leakage, for example, in SoC device SRAM circuits in a manner that is independent of the read/write/standby operating mode, and without an external trigger. Wordline-driver-biasing circuitry turns off (i.e., decouples from system power) wordline-drivers that are connected to unselected wordlines during read/write operations using one of a decoder-enable signal, which is generated in response to…
LOW POWER DIGITAL FRACTIONAL DIVIDER WITH GLITCHLESS OUTPUT
Granted: March 12, 2015
Application Number:
20150071393
A digital circuit that divides a high speed digital clock by a fractional value is described. The circuit utilizes a divider circuit and shifts the divider clock by a fraction of a phase to achieve the desired fractional division. A clock mux is used to perform the clock shift, and a masking mux is used to eliminate glitches during the clock shift.
HIGH SPEED PHASE SELECTOR WITH A GLITCHLESS OUTPUT USED IN PHASE LOCKED LOOP APPLICATIONS
Granted: March 12, 2015
Application Number:
20150070051
A digital phase selector circuit that switches an output clock between N input clock phases is described. The phase selector utilizes a special output mux and switches clock phases during a safe zone to avoid glitches. The phase selector is used in the feedback path of a PLL to implement functions such as spread spectrum or fractional reference clocks. An example with N=4 and an optimized latch mux is shown.
DIAGNOSIS AND DEBUG USING TRUNCATED SIMULATION
Granted: March 5, 2015
Application Number:
20150067629
Patterns used to detect a failure in a semiconductor chip are analyzed to determine a subset of logic in a design where a semiconductor chip, fabricated based on the design, contains a fault in the subset. Parts of the semiconductor chip can be pre-calculated to identify a key subsection of logic, based on the patterns, with that subsection being stored in a computer readable file. Good-machine simulation is performed on the subsection of logic using truncated rank-ordered simulation.…
Deferred Execution in a Multi-thread Safe System Level Modeling Simulation
Granted: February 26, 2015
Application Number:
20150058859
Methods, systems, and machine readable medium for multi-thread safe system level modeling simulation (SLMS) of a target system on a host system. An example of a SLMS is a SYSTEMC simulation. During the SLMS, SLMS processes are executed in parallel via a plurality of threads. SLMS processes represent functional behaviors of components within the target system, such as functional behaviors of processor cores. Deferred execution may be used to defer execution of operations of SLMS processes…
Direct Memory Interface Access in a Multi-Thread Safe System Level Modeling Simulation
Granted: February 26, 2015
Application Number:
20150058854
Methods, systems, and machine readable medium for multi-thread safe system level modeling simulation (SLMS) of a target system on a host system. An example of a SLMS is a SYSTEMC simulation. During the SLMS, SLMS processes are executed in parallel via a plurality of threads. SLMS processes represent functional behaviors of components within the target system, such as functional behaviors of processor cores. Deferred execution may be used to defer execution of operations of SLMS processes…
Guarded Memory Access in a Multi-Thread Safe System Level Modeling Simulation
Granted: February 26, 2015
Application Number:
20150058586
Methods, systems, and machine readable medium for multi-thread safe system level modeling simulation (SLMS) of a target system on a host system. An example of a SLMS is a SYSTEMC simulation. During the SLMS, SLMS processes are executed in parallel via a plurality of threads. SLMS processes represent functional behaviors of components within the target system, such as functional behaviors of processor cores. Deferred execution may be used to defer execution of operations of SLMS processes…
GENERALIZED MOMENT BASED APPROACH FOR VARIATION AWARE TIMING ANALYSIS
Granted: February 12, 2015
Application Number:
20150046897
A method and apparatus of a device that performs a generalized moment based variation aware timing analysis on a circuit design is described. The device receives a signal path that traverses a plurality of gates. For each of the plurality of gates, the device retrieves a statistical distribution that represents delay variation at the gate. The statistical distribution for each gate is measured by a number of statistical moments that include higher order statistical moments besides the…
N-CHANNEL AND P-CHANNEL END-TO-END FINFET CELL ARCHITECTURE
Granted: February 12, 2015
Application Number:
20150041924
A finFET block architecture uses end-to-end finFET blocks. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. An inter-block isolation structure separates the semiconductor fins in the first and second sets. The ends of the fins in the first set are proximal to a first side of the inter-block isolation structure and ends of the fins in the second set are proximal to a…
INCREASING ION/IOFF RATIO IN FINFETS AND NANO-WIRES
Granted: February 12, 2015
Application Number:
20150041921
Roughly described, an integrated circuit transistor structure has a body of semiconductor material, the body having two longitudinally spaced doped source/drain volumes with a channel between, a gate stack disposed outside the body and facing at least one of the surfaces of the body along the channel. The body contains an adjustment volume, longitudinally within the channel volume and spaced behind the first surface by a first distance and spaced longitudinally from both the source/drain…
Efficient Complex Multiplication and Fast Fourier Transform (FFT) Implementation on the ManArray Architecture
Granted: February 5, 2015
Application Number:
20150039856
Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with specialized complex multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs are used allowing the complex multiplication pipeline…
EMULATION-BASED FUNCTIONAL QUALIFICATION
Granted: February 5, 2015
Application Number:
20150040096
Techniques for emulation-based functional qualification are disclosed that use an emulation platform to replace simulation in mutation-based analysis. A method for functional qualification of an integrated circuit design includes receiving an integrated circuit design having one or more mutations. Emulation setup and activation simulation are performed in parallel to maximize computing resources. A prototype board can then be programmed according to the integrated circuit design and a…
ROBUST NUMERICAL OPTIMIZATION FOR OPTIMIZING DELAY, AREA, AND LEAKAGE POWER
Granted: February 5, 2015
Application Number:
20150040093
Systems and techniques are described for performing numerical delay, area, and leakage power optimization on a circuit design. During operation, an embodiment can iteratively perform at least the following set of operations in a loop, wherein in each iteration a current threshold voltage value is progressively decreased: (a) perform numerical delay optimization on the circuit design using a numerical delay model that is generated using gates in a technology library whose threshold…
DISCRETIZING GATE SIZES DURING NUMERICAL SYNTHESIS
Granted: February 5, 2015
Application Number:
20150040090
Systems and techniques are described for discretizing gate sizes during numerical synthesis. Some embodiments can receive an optimal input capacitance value for an input of an optimizable cell, wherein the input capacitance value is determined by a numerical solver that is optimizing the circuit design. Note that the circuit design may be optimized for different objective functions, e.g., best delay, minimal area under delay constraints, etc. Next, the embodiments can identify an initial…
