EMULATION-BASED FUNCTIONAL QUALIFICATION
Granted: February 5, 2015
Application Number:
20150040096
Techniques for emulation-based functional qualification are disclosed that use an emulation platform to replace simulation in mutation-based analysis. A method for functional qualification of an integrated circuit design includes receiving an integrated circuit design having one or more mutations. Emulation setup and activation simulation are performed in parallel to maximize computing resources. A prototype board can then be programmed according to the integrated circuit design and a…
ROBUST NUMERICAL OPTIMIZATION FOR OPTIMIZING DELAY, AREA, AND LEAKAGE POWER
Granted: February 5, 2015
Application Number:
20150040093
Systems and techniques are described for performing numerical delay, area, and leakage power optimization on a circuit design. During operation, an embodiment can iteratively perform at least the following set of operations in a loop, wherein in each iteration a current threshold voltage value is progressively decreased: (a) perform numerical delay optimization on the circuit design using a numerical delay model that is generated using gates in a technology library whose threshold…
DISCRETIZING GATE SIZES DURING NUMERICAL SYNTHESIS
Granted: February 5, 2015
Application Number:
20150040090
Systems and techniques are described for discretizing gate sizes during numerical synthesis. Some embodiments can receive an optimal input capacitance value for an input of an optimizable cell, wherein the input capacitance value is determined by a numerical solver that is optimizing the circuit design. Note that the circuit design may be optimized for different objective functions, e.g., best delay, minimal area under delay constraints, etc. Next, the embodiments can identify an initial…
Efficient Complex Multiplication and Fast Fourier Transform (FFT) Implementation on the ManArray Architecture
Granted: February 5, 2015
Application Number:
20150039856
Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with specialized complex multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs are used allowing the complex multiplication pipeline…
METHOD AND APPARATUS FOR SECURING CONFIGURATION SCAN CHAINS OF A PROGRAMMABLE DEVICE
Granted: January 29, 2015
Application Number:
20150033360
Scan chain circuitry on an integrated circuit device includes a plurality of memory elements, and a plurality of control elements. Each of the control elements is located between respective ones of the plurality of memory elements for controllably connecting the plurality of memory elements into a scan chain. A plurality of respective scan enable activation elements controls a respective subplurality of the plurality of control elements for connecting a respective subplurality of the…
CACHE DEBUG SYSTEM FOR PROGRAMMABLE CIRCUITS
Granted: January 29, 2015
Application Number:
20150033075
An integrated circuit may be provided with system-on-chip circuitry including system-on-chip interconnects and a microprocessor unit subsystem. The subsystem may include microprocessor cores that execute instructions stored in memory. Cache may be used to cache data for the microprocessor cores. A memory coherency control unit may be used to maintain memory coherency during operation of the microprocessor unit subsystem. The memory coherency control unit may be coupled to the…
ERROR RESILIENT PACKAGED COMPONENTS
Granted: January 29, 2015
Application Number:
20150028918
A packaged component may include an interposer and integrated circuit dies mounted on the interposer. At least one of the dies may be a radiation-hardened integrated circuit die, whereas the remaining dies may be non-radiation-hardened dies. If desired, the interposer may be a radiation-hardened interposer whereas the integrated circuit dies may be non-radiation-hardened dies. The radiation-hardened die or the radiation-hardened interposer may include monitor circuitry that is used to…
PROCESSORS OPERABLE TO ALLOW FLEXIBLE INSTRUCTION ALIGNMENT
Granted: January 29, 2015
Application Number:
20150032995
Methods and apparatus are provided for optimizing a processor core. Common processor subcircuitry is used to perform calculations for various types of instructions, including branch and non-branch instructions. Increasing the commonality of calculations across different instruction types allows branch instructions to jump to byte aligned memory address even if supported instructions are multi-byte or word aligned.
LITHOGRAPHIC HOTSPOT DETECTION USING MULTIPLE MACHINE LEARNING KERNELS
Granted: December 4, 2014
Application Number:
20140358830
A hotspot detection system that classifies a set of hotspot training data into a plurality of hotspot clusters according to their topologies, where the hotspot clusters are associated with different hotspot topologies, and classifies a set of non-hotspot training data into a plurality of non-hotspot clusters according to their topologies, where the non-hotspot clusters are associated with different topologies. The system extracts topological and non-topological critical features from the…
EQUIVALENCE CHECKING USING STRUCTURAL ANALYSIS ON DATA FLOW GRAPHS
Granted: December 4, 2014
Application Number:
20140359545
A design is verified by using equivalence checking to compare a word-level description of the design to a bit-level description of the design. A word-level data flow graph (DFG) based on the word-level description and a bit-level DFG is obtained. Structural analysis is used to reduce the graphs and partition them into smaller portions for the equivalence checking. The analysis includes searching the bit-level DFG to find partial-product encoding and removing redundancy from the bit-level…
ON-CHIP INDUCTORS WITH REDUCED AREA AND RESISTANCE
Granted: November 27, 2014
Application Number:
20140346634
An integrated circuit that includes an on-chip inductor wrapped around an interface pad. On-chip inductors are arranged around an interface pad to reduce the area occupied by the inductor. Furthermore, arranging the on-chip inductors in an upper level metal layer, such us the redistribution layer (RDL), the top metal interconnect layer (MTop), or the second-to-top metal interconnect layer (MTop-1) reduces the on-chip inductor parasitic resistance, reducing the loss of signal.
SEQUENTIAL LOGIC SENSITIZATION FROM STRUCTURAL DESCRIPTION
Granted: November 20, 2014
Application Number:
20140344637
A method of sensitizing a sequential circuit is described. This sensitizing generates stimuli to drive any circuit output to a predetermined value or transition. The method includes creating a directed graph of the sequential circuit. Nodes of the graphs can be topologically sorted. In one embodiment, feedback loops in the directed graph can be removed before topologically sorting the nodes. Final vectors for the sequential circuit can be generated based on the sorted nodes. Notably, the…
SEMI-LOCAL BALLISTIC MOBILITY MODEL
Granted: November 20, 2014
Application Number:
20140344772
A transistor model defines the carrier mobility as a combination of both drift-diffusion mobility and ballistic mobility. The ballistic mobility is calculated based on the assumption that the kinetic energy of carriers near an injection point is no greater than the potential energy difference of carriers near that injection point. The abruptness of the onset of velocity saturation, as well as the asymptotic velocity associated therewith is made dependent on the degree to which the…
SUB-MODULE PHYSICAL REFINEMENT FLOW
Granted: November 13, 2014
Application Number:
20140337811
A computer system is provided that enables a designer of a circuit design to fracture and reconstitute a larger design for both computer modeling of the functionality and the physical implementation or rendering of the circuit design. More particularly, the designer may refine or re-work a sub-module of the larger sub-circuit without having to create a corresponding sub-module in the physical implementation. This capability thus avoids the significant complexity required for sub-module…
FORMAL VERIFICATION RESULT PREDICTION
Granted: November 6, 2014
Application Number:
20140330758
A design verification problem includes a design description and a property to be verified. Feature data is identified from the design verification problem and a result is predicted for the design verification problem based on the feature data. A plurality of verification engines is then orchestrated based on the prediction. Supervised machine learning may be used for the result prediction. Feature data and verification results from a plurality of training test cases are used to train a…
MANIPULATING PARAMETERIZED CELL DEVICES IN A CUSTOM LAYOUT DESIGN
Granted: October 9, 2014
Application Number:
20140304671
A system, apparatus and computer-implemented method for manipulating a parameterized cell device into a custom layout design. The method begins by receiving at least one parameterized cell representing a physical circuit from, for example, a database or configuration file. The parameterized cell has a plurality of configurable attributes. The method continues by adjusting one of the configurable attributes of the parameterized cell according to a capability associated with the one…
DUAL-STRUCTURE CLOCK TREE SYNTHESIS (CTS)
Granted: September 25, 2014
Application Number:
20140289694
Dual-structure clock tree synthesis (CTS) is described. Some embodiments can construct a set of upper-level clock trees, wherein each leaf of each upper-level clock tree is a root of a lower-level clock tree. Each upper-level clock tree can be optimized to reduce an impact of on-chip-variation and/or cross-corner variation on clock skew. Next, for each leaf of each upper-level clock tree, the embodiments can construct a lower-level clock tree to distribute a clock signal from the leaf of…
ON-CHIP-VARIATION (OCV) AND TIMING-CRITICALITY AWARE CLOCK TREE SYNTHESIS (CTS)
Granted: September 25, 2014
Application Number:
20140289690
On-chip-variation (OCV) and timing-criticality aware clock tree synthesis (CTS) is described. Some embodiments can construct a first set of clock tree topologies for timing sequential circuit elements in a set of critical paths, wherein said constructing can comprise optimizing the first set of clock tree topologies to reduce an impact of OCV on clock skew. Next, the embodiments can construct a second set of clock tree topologies for timing sequential circuit elements that are not in the…
DYNAMIC POWER DRIVEN CLOCK TREE SYNTHESIS (CTS)
Granted: September 25, 2014
Application Number:
20140289685
Dynamic power driven clock tree synthesis is described. Some embodiments can select one or more cells from a cell library based on power ratios of cells in the cell library. The embodiments can then construct a clock tree based on the one or more cells.
Scheduling in a multicore architecture
Granted: September 18, 2014
Application Number:
20140282593
The disclosure relates to scheduling threads in a multicore processor. Executable transactions may be scheduled using at least one distribution queue, which lists executable transactions in order of eligibility for execution, and multilevel scheduler which comprises a plurality of linked individual executable transaction schedulers. Each of these includes a scheduling algorithm for determining the most eligible executable transaction for execution. The most eligible executable…
