SUB-RESOLUTION ASSIST FEATURE IMPLEMENTATION USING SHOT OPTIMIZATION
Granted: September 18, 2014
Application Number:
20140282290
A design layout for a semiconductor chip includes information on shapes desired to be fabricated. Clusters of photolithographic exposure “shots” are generated and subject to a measure of shot density to approximate a mask shape that generates the desired fabricated shapes when exposed during wafer fabrication. A simulation is run on the clusters of shots to estimate the resulting fabrication shapes that the clusters of shots create. The clusters of shots are modified to align the…
Scheduling in a multicore architecture
Granted: September 18, 2014
Application Number:
20140282593
The disclosure relates to scheduling threads in a multicore processor. Executable transactions may be scheduled using at least one distribution queue, which lists executable transactions in order of eligibility for execution, and multilevel scheduler which comprises a plurality of linked individual executable transaction schedulers. Each of these includes a scheduling algorithm for determining the most eligible executable transaction for execution. The most eligible executable…
AUTOMATIC CLOCK TREE SYNTHESIS EXCEPTIONS GENERATION
Granted: September 18, 2014
Application Number:
20140282350
Systems and techniques are described for automatically generating clock tree synthesis (CTS) exceptions. The process can use on one or more criteria to identify sequential circuit elements that can be ignored during clock skew minimization. For example, the process can identify sequential circuit elements whose clock skew cannot be balanced with other sequential circuit elements due to structural reasons, identify sequential timing elements that do not have a timing relationship with…
PRIORITIZED SOFT CONSTRAINT SOLVING
Granted: September 18, 2014
Application Number:
20140282343
A design problem can include a mixture of hard constraints and soft constraints. The soft constraints can be prioritized and the design problem solved. One or more soft constraints may not be honored in the midst of the solving of the design problem. Debugging can be performed and the unsatisfied soft constraints identified. Root-cause analysis can evaluate the challenges within the design problem which caused soft constraints not to be honored.
AUTOMATIC TAP DRIVER GENERATION IN A HYBRID CLOCK DISTRIBUTION SYSTEM
Granted: September 18, 2014
Application Number:
20140282339
A hybrid clock distribution system uses a distribution fabric to distribute clock signals across longer physical distances and local sub-distribution networks to distribute clock signals more locally and to implement logic functions such as clock gating. A set of tap drivers connect the distribution fabric to the sub-distribution networks. A design tool automatically generates and places the set of tap drivers.
PHASE DETERMINATION FOR EXTRACTION FROM SCATTERING PARAMETERS
Granted: September 18, 2014
Application Number:
20140282335
Scattering (S) parameters can be evaluated for a plurality of conductors on a semiconductor device to determine phase based on traversal around a Smith chart type representation. A propagation function for the plurality of conductors can be derived from S parameters, which in turn, can be used to derive resistance, inductance, capacitance, and/or conductance parameters. A Smith chart representation is used to obtain zero crossing information for determination of accurate phase…
ARRIVAL EDGE USAGE IN TIMING ANALYSIS
Granted: September 18, 2014
Application Number:
20140282317
A logic design is analyzed using static timing analysis and timing edge tracking for various nets within the logic design. Crosstalk analysis is performed on the logic design to evaluate timing impacts. To reduce pessimism of crosstalk analysis for a victim net, arrival edges are tracked for the victim net. The switching times of the aggressor net are compared to the edges of the victim net during crosstalk analysis.
SOLVING MULTIPLICATION CONSTRAINTS BY FACTORIZATION
Granted: September 18, 2014
Application Number:
20140282316
A design description for verification includes a set of constraints on random variables within the design description. The set of constraints includes at least one multiplication constraint involving at least two random variables. A computer-based tool obtains designs and analyzes the design description to find the set of constraints and identify the multiplication constraint. The computer-based tool then performs factorization to solve for the multiplication constraint and to determine…
GRAPHICAL VIEW AND DEBUG FOR COVERAGE-POINT NEGATIVE HINT
Granted: September 18, 2014
Application Number:
20140282315
The present invention provides a graphical view of this connected network that allows the user to navigate throughout a network. The graph view consists of a series of nodes that correspond to a set of test, testbench, design or coverage items in the simulation. Various nodes in the network are colored or shaped differently to represent either test, class, stimulus, testbench, design or coverage points. The graph may be drawn so that all items that occur at the same time are lined up in…
PERFORMING IMAGE CALCULATION BASED ON SPATIAL COHERENCE
Granted: September 18, 2014
Application Number:
20140282298
Computer-implemented techniques for pixel source optics calculations using spatial coherence are disclosed. Pixelated sources are used for source-mask co-optimization to enhance semiconductor lithography. Calculation of a partially coherent imaging system is used for optical-lithography simulation. The spatial coherence property of neighboring source points is used to reduce imaging calculation complexity. Two or more neighboring points are treated as one pseudo-spatially coherent area…
Localizing Fault Flop in Circuit by Using Modified Test Pattern
Granted: September 18, 2014
Application Number:
20140281777
A method for localizing at least one scan flop associated with a fault in an integrated circuit. A first test pattern, including a first scan-in data and first control data, is generated. Based on the first control data of the first test pattern, a first fault data is generated by applying the first scan-in data of the first test pattern to scan flops in a test circuit of the integrated circuit. If the first fault data indicates that a fault may be present in the integrated circuit, a…
Two-Level Compression Through Selective Reseeding
Granted: September 18, 2014
Application Number:
20140281774
A scan test system and technique compresses CARE bits and X-control input data into PRPG seeds, thereby providing a first compression. The scan test system includes a plurality of compressor and decompressor structures (CODECs). Each block of the design includes at least one CODEC. An instruction decode unit (IDU) receives scan inputs and determines whether a seed extracted from the scan inputs is broadcast loaded in the CODECs, multicast loaded in a subset of the CODECs, or individual…
Memory Interface and Method of Interfacing Between Functional Entities
Granted: September 18, 2014
Application Number:
20140281114
A data and signal interface for controlling the transfer of data and signals between a memory array and macro function such as that of a digital signal processor (DSP) core. In one embodiment, the interface comprises a plurality of memory ports which interface with X/Y memory banks, a plurality of function ports, each with a function controller, which interface with DSP functions, a crossbar connecting the memory and function ports, and an arbitration unit for arbitrating memory access…
Specification-Guided User Interface for Optical Design Systems
Granted: September 18, 2014
Application Number:
20140278263
An optical design system generates a design state overview of a design of an optical system, the design state overview summarizing a current state and a target state of the design by describing a plurality of specifications for the optical system, the specification descriptions including target ranges for the specifications based on the target state of the design and further including current values for the specifications based on the current state of the design. The optical design…
LOW VOLTAGE LEVEL SHIFTER FOR LOW POWER APPLICATIONS
Granted: September 11, 2014
Application Number:
20140253211
A level shifter circuit for low power applications that can shift the level of a digital signal that is below the threshold voltage of output transistors. The level shifter uses core transistors in the input stage and includes an intermediate stage that limits the voltage applied to the drain of the core transistors. The intermediate stage may include two transistors whose gate is connected to a reference voltage and turns off when the voltage at their source is equal to a threshold…
AUTOMATIC SYNTHESIS OF COMPLEX CLOCK SYSTEMS
Granted: September 11, 2014
Application Number:
20140258964
A global optimization method to synthesize and balance the clock systems in a multimode, multi-corner, and multi-domain design environment is described. The method builds a graph representation for a clock network. The method determines an optimal clock network balancing solution for the clock network by applying linear programming to the graph. To apply linear programming to the graph, the method generates a set of constraints for the graph and determines a proper insertion delay for…
PLACEMENT AND ROUTING ON A CIRCUIT
Granted: September 11, 2014
Application Number:
20140258963
Methods and apparatuses to place and route cells on integrated circuit chips along paths is described. In one embodiment, the method to layout an integrated circuit, the method comprises routing a wire to connect a first cell of the integrated circuit and a second cell of the integrated circuit, and placing a third cell of the integrated circuit after said routing the wire to connect the first cell and the second cell.
RANKING VERIFICATION RESULTS FOR ROOT CAUSE ANALYSIS
Granted: September 11, 2014
Application Number:
20140258954
Verification-result ranking techniques for root cause analysis are disclosed using violation report analysis and violation weighting. Violation reports are unwieldy and result from a variety of design and process checks. The check coverage can overlap, causing a specific violation to trigger multiple reported violations. High turn around times for violation report analysis increase the risk that selective violation analysis will inadvertently suppress real design bugs. This reduces the…
HIGH PERFORMANCE DESIGN RULE CHECKING TECHNIQUE
Granted: September 11, 2014
Application Number:
20140258953
Roughly described, a design rule data set is developed offline from the design rules of a target fabrication process. A design rule checking method involves traversing the corners of shapes in a layout region, and for each corner, populating a layout topology database with values that depend on respective corner locations. After the layout topology database is populated, the values are compared to values in the design rule data set to detect any design rule violations. Violations can be…
METHOD AND APPARATUS FOR PROCESS WINDOW MODELING
Granted: September 11, 2014
Application Number:
20140257544
A photolithographic modeling process is disclosed. Optical and non-optical parts of a model of the photolithographic process are calibrated. With the non-optical part of the model one or more model corrections are determined between (i) modeled critical dimension data from an aerial image generated by the optical part of the model, and (ii) empirical critical dimension data from tangible structures made at only a first process combination of a first dose and a first defocus in the…
