DETECTION AND REMOVAL OF SELF-ALIGNED DOUBLE PATTERNING ARTIFACTS
Granted: August 28, 2014
Application Number:
20140245239
Mask design techniques for detection and removal of undesirable artifacts in SADP processes using multiple patterns are disclosed. Artifacts or spurs result from lithographic and chemical processing of semiconducting wafers. The spurs are undesirable because they can cause unwanted connections or act as electrical antennas. Spurs are detected using rule-based techniques and reduced by modifying lithographic masks. The severity of the detected spurs is determined, again using rule-based…
HYBRID EVOLUTIONARY ALGORITHM FOR TRIPLE-PATTERNING
Granted: August 28, 2014
Application Number:
20140245237
According to one embodiment of the present invention, a computer-implemented method for validating a design includes generating, using the computer, a first graph representative of the design, when the computer is invoked to validate the design, and decompose, using the computer, the first graph into at least three sets using a hybrid evolutionary algorithm to form a colored graph.
EXECUTING A HARDWARE SIMULATION AND VERIFICATION SOLUTION
Granted: August 28, 2014
Application Number:
20140244233
One embodiment of the present invention provides systems and techniques to execute a hardware simulation and verification solution on a multiprocessor system. The hardware simulation and verification solution can be partitioned into different modules which can include a simulation kernel to simulate changes in signal values, a value change dump module to store the changes in the signal values on a computer-readable storage medium, a functional coverage module to check functionality, a…
COMPACT OPC MODEL GENERATION USING VIRTUAL DATA
Granted: August 28, 2014
Application Number:
20140244226
A method, system or computer usable program product for building a fast lithography OPC model that predicts semiconductor manufacturing process outputs on silicon wafers including providing a first principles model of the semiconductor manufacturing process, providing a set of empirical data for storage in memory, utilizing a processor to develop a rigorous model for a process condition from the first principles model and the set of empirical data, and utilizing the processor running the…
LOOK-UP BASED FAST LOGIC SYNTHESIS
Granted: August 21, 2014
Application Number:
20140237437
Systems and techniques are described for performing circuit synthesis. Some embodiments create a lookup table based on information contained in a cell library. The lookup table is then used during circuit synthesis. Specifically, some embodiments optimize cells in a reverse-levelized cell ordering. For a given cell, a table lookup is performed to obtain a set of optimal cell configurations, and the cell is replaced with a cell configuration selected from the set of optimal cell…
METHOD FOR MANAGING DESIGN FILES SHARED BY MULTIPLE USERS AND SYSTEM THEREOF
Granted: August 21, 2014
Application Number:
20140237006
A method for managing design files shared by multiple users is provided. A plurality of design files are stored in a design library. A lock table is moved to a memory of a first computer when information of the lock table indicates that the design files were locked by a first process corresponding to a first user, wherein the memory is only accessible to performance of the first process. The lock table is moved from the memory to a common memory of the first computer when one design file…
Power Routing in Standard Cells
Granted: August 14, 2014
Application Number:
20140229908
An integrated circuit created from a cell library of compact cells. The cell library includes cells having a metal trace routed along the boundary of the cells for carrying a power supply voltage. The cells also include another metal trace routed along the interior of the cells for carrying another power supply voltage. A cell pin carrying an input signal or output signal of the cell is located outside of the region between the two power rails. By routing the power supply voltages and…
BOOSTING TRANSISTOR PERFORMANCE WITH NON-RECTANGULAR CHANNELS
Granted: August 7, 2014
Application Number:
20140223395
Roughly described, the invention includes layouts and masks for an integrated circuit, in which the diffusion shape for a transistor includes a transversely extending jog on one or both transversely opposite sides, the jog having inner and outer corners, at least one of which is located relative to the gate conductor longitudinally such that during lithographic printing of the diffusion shape onto the integrated circuit, the corner will round and extend at least partly into the channel…
NUMERICAL DELAY MODEL FOR A TECHNOLOGY LIBRARY CELL TYPE
Granted: August 7, 2014
Application Number:
20140223400
Methods and systems for determining a numerical delay model based on one or more discretized delay models are described. A discretized delay model is a delay model in which the delay behavior is represented using a set of discrete data points of delay behavior. A numerical delay model is a delay model that can be used by a numerical solver to optimize a cost function. In general, computing delay using a numerical delay model is significantly faster than computing delay using discretized…
METHODS FOR MANUFACTURING INTEGRATED CIRCUIT DEVICES HAVING FEATURES WITH REDUCED EDGE CURVATURE
Granted: August 7, 2014
Application Number:
20140223394
A structure, such as an integrated circuit device, is described that includes a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in etching the line. Techniques are described for processing a line of crystalline phase material which has already been etched using the mask element, in a manner which straightens an etched sidewall surface of the line. The straightened sidewall…
N-CHANNEL AND P-CHANNEL END-TO-END FINFET CELL ARCHITECTURE WITH RELAXED GATE PITCH
Granted: August 7, 2014
Application Number:
20140217514
A finFET block architecture uses end-to-end finFET blocks in which the fin lengths are at least twice the contact pitch, whereby there is enough space for interlayer connectors to be placed on the proximal end and the distal end of a given semiconductor fin, and on the gate element on the given semiconductor fin. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. Interlayer…
Optimizing Designs of Integrated Circuits
Granted: July 31, 2014
Application Number:
20140215427
Methods and systems for optimizing and/or designing integrated circuits. One exemplary method includes determining fanout of a driving component in a representation of an integrated circuit (IC) being designed, determining for the driving component, the loads in the representation of the IC driven by the driving component, and determining use of existing wiring resources used to connect the loads to the driving component. The method further includes optimizing, based on the use of…
MODELING MECHANICAL BEHAVIOR WITH LAYOUT-DEPENDENT MATERIAL PROPERTIES
Granted: July 24, 2014
Application Number:
20140208280
Computer-implemented techniques for modeling the mechanical behavior of integrated circuits using layout-dependent material properties are disclosed. The back end of line wiring that connects an integrated circuit to a substrate undergoes stresses and strains due to many heating and cooling cycles during a chip's packaging and lifecycle. Depending on integrated circuit design style, there may be vastly different thermal profiles across the integrated circuit. The mechanical behavior…
MICROPROCESSOR ARCHITECTURE HAVING EXTENDIBLE LOGIC
Granted: July 24, 2014
Application Number:
20140208087
A microprocessor architecture having extendible logic. One or more customized applications are available to the instruction pipeline. The customizable applications may include software, extension logic instruction or register, dynamically configurable hardware logic, or combinations of these. In order to enable the operating system to interface with the customized extension applications, at least one software extension is provided to the operating system. When a specific extension is…
System and Method of Debugging Multi-Threaded Processes
Granted: July 10, 2014
Application Number:
20140196014
A system and method of debugging a multi-threaded process with at least one running thread and at least one suspended thread is disclosed. Embodiments utilize a blocking function to block the thread of a process while other threads are allowed to run. The blocking function may be executed in a suspended thread by a debugger under control of a thread blocking controller. The other threads may implement interprocess communication channels for enabling communication between the process and…
INCREMENTAL CONCURRENT PROCESSING FOR EFFICIENT COMPUTATION OF HIGH-VOLUME LAYOUT DATA
Granted: July 3, 2014
Application Number:
20140189616
Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, different data processing stages can partition the layout data…
PATTERN-BASED POWER-AND-GROUND (PG) ROUTING AND VIA CREATION
Granted: July 3, 2014
Application Number:
20140189629
Systems and techniques for pattern-based power-and-ground (PG) routing and via rule based via creation are described. A pattern for routing PG wires can be received. Next, an instantiation strategy may be received, wherein the instantiation strategy specifies an area of an integrated circuit (IC) design layout where PG wires based on the pattern are to be instantiated and specifies one or more net identifiers that are to be assigned to the instantiated PG wires. The PG wires can be…
ABSTRACT CREATION
Granted: July 3, 2014
Application Number:
20140189624
Systems and techniques for creating a circuit abstraction are described. During operation, an embodiment can identify a set of side loads based on a set of timing paths. According to one definition, a side load of a timing path is a circuit element that is not on the timing path (i.e., the timing path does not pass through the circuit element), but whose input is electrically connected to an output of at least one circuit element that is on the timing path. Next, the embodiment can…
NETLIST ABSTRACTION
Granted: July 3, 2014
Application Number:
20140189620
Systems and techniques for creating a netlist abstraction are described. During operation, an embodiment can receive a netlist for a circuit design, wherein circuit elements in the circuit design are organized in a logical hierarchy (LH). Next, the embodiment can receive a set of LH nodes in the LH. The embodiment can then create the netlist abstraction by, for each LH node in the set of LH nodes, replacing a portion of the netlist that is below the LH node by a star netlist, wherein the…
DISPLAYING A CONGESTION INDICATOR FOR A CHANNEL IN A CIRCUIT DESIGN LAYOUT
Granted: July 3, 2014
Application Number:
20140189617
Methods and apparatuses are described for creating, editing, and viewing a floorplan of a circuit design. Specifically, some embodiments enable a user to perform a graphical operation at an inference point in a circuit design layout, wherein the location of the inference point is determined based on existing graphical objects in the circuit design layout. Some embodiments substantially instantaneously update a congestion indicator in a circuit design layout in response to modifying the…
