NETLIST ABSTRACTION
Granted: July 3, 2014
Application Number:
20140189620
Systems and techniques for creating a netlist abstraction are described. During operation, an embodiment can receive a netlist for a circuit design, wherein circuit elements in the circuit design are organized in a logical hierarchy (LH). Next, the embodiment can receive a set of LH nodes in the LH. The embodiment can then create the netlist abstraction by, for each LH node in the set of LH nodes, replacing a portion of the netlist that is below the LH node by a star netlist, wherein the…
DISPLAYING A CONGESTION INDICATOR FOR A CHANNEL IN A CIRCUIT DESIGN LAYOUT
Granted: July 3, 2014
Application Number:
20140189617
Methods and apparatuses are described for creating, editing, and viewing a floorplan of a circuit design. Specifically, some embodiments enable a user to perform a graphical operation at an inference point in a circuit design layout, wherein the location of the inference point is determined based on existing graphical objects in the circuit design layout. Some embodiments substantially instantaneously update a congestion indicator in a circuit design layout in response to modifying the…
INCREMENTAL CONCURRENT PROCESSING FOR EFFICIENT COMPUTATION OF HIGH-VOLUME LAYOUT DATA
Granted: July 3, 2014
Application Number:
20140189616
Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, different data processing stages can partition the layout data…
Structured Block Transfer Module, System Architecture, and Method for Transferring
Granted: June 26, 2014
Application Number:
20140181447
Structured block transfer module, system architecture, and method for transferring content or data. Circuit allowing content in one memory to be shifted, moved, or copied to another memory with no direction from a host, the circuit comprising: a connection manager, at least one copy engine, and a connection between the connection manager and the copy engine. Method for transferring the contents of one of a number of blocks of source memory to one of a number of possible destination…
TIMING BOTTLENECK ANALYSIS ACROSS PIPELINES TO GUIDE OPTIMIZATION WITH USEFUL SKEW
Granted: June 26, 2014
Application Number:
20140181779
Techniques and systems for guiding circuit optimization are described. Some embodiments compute a set of aggregate slacks for a set of chains of logic paths in a circuit design. Each chain of logic paths starts from a primary input or a sequential circuit element that only launches a signal but does not capture a signal and ends at a primary output or a sequential circuit element that only captures a signal but does not launch a signal. Next, the embodiments guide circuit optimization of…
AUTOMATIC CLOCK TREE ROUTING RULE GENERATION
Granted: June 26, 2014
Application Number:
20140181777
Systems and techniques are described for automatically generating a set of non-default routing rules for routing a net in a clock tree based on one or more metrics. The metrics can include a congestion metric, a latency metric, a crosstalk metric, an electromigration metric, and a clock tree level. Next, the embodiments can generate the set of non-default routing rules for routing the net based on one or more metrics. A routing rule can specify how wide the wires are supposed to be and…
WHAT-IF PARTITIONING AND TIMING
Granted: June 26, 2014
Application Number:
20140181776
Methods and apparatuses are described for facilitating a user to explore and evaluate different options during floorplanning. Some embodiments display a graphical representation of a circuit design floorplan, wherein the graphical representation includes a set of blocks and a set of flylines between blocks, wherein each block corresponds to a portion of the circuit design, and wherein each flyline corresponds to one or more relationships between two blocks. Additionally, a set of metrics…
SHAPING INTEGRATED WITH POWER NETWORK SYNTHESIS (PNS) FOR POWER GRID (PG) ALIGNMENT
Granted: June 26, 2014
Application Number:
20140181773
Embodiments are described in which shaping is integrated with power network synthesis (PNS) for power grid (PG) alignment. Specifically, some embodiments create placement constraints based on the PG that is expected to be created by PNS, and then perform shaping (or perform legalization) on the circuit design based on the placement constraints. This ensures that the physical partitions (e.g., instances of multiply-instantiated-blocks) are aligned with the power grid during shaping.
MULTI-MODE SCHEDULER FOR CLOCK TREE SYNTHESIS
Granted: June 26, 2014
Application Number:
20140181766
Techniques and systems for performing clock tree synthesis (CTS) across multiple modes are described. Some embodiments traverse one or more clock trees from the root of each clock tree to a set of sinks of the clock tree. During the traversal, each clock gate can be marked with a traversal level, and each sink can be marked with one or more clocks and one or more modes that are associated with the sink. A task queue can then be created based on the information collected during the clock…
LOOK-UP BASED BUFFER TREE SYNTHESIS
Granted: June 26, 2014
Application Number:
20140181765
Systems and techniques are described for performing buffer tree synthesis. Some embodiments create a lookup table based on information contained in a cell library. The lookup table is then used during buffer tree synthesis.
Structured Block Transfer Module, System Architecture, and Method for Transferring
Granted: June 26, 2014
Application Number:
20140181343
Structured block transfer module, system architecture, and method for transferring content or data. Circuit allowing content in one memory to be shifted, moved, or copied to another memory with no direction from a host, the circuit comprising: a connection manager, at least one copy engine, and a connection between the connection manager and the copy engine. Method for transferring the contents of one of a number of blocks of source memory to one of a number of possible destination…
PLACING TRANSISTORS IN PROXIMITY TO THROUGH-SILICON VIAS
Granted: June 19, 2014
Application Number:
20140173545
Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the…
STATISTICAL FORMAL ACTIVITY ANALYSIS WITH CONSIDERATION OF TEMPORAL AND SPATIAL CORRELATIONS
Granted: June 12, 2014
Application Number:
20140165024
Techniques for statistical formal activity analysis with consideration of temporal and/or spatial correlations are described herein. According to one embodiment, a machine-implemented method for circuit analysis comprises unrolling a sequential circuit having a feedback loop into a plurality of unrolled circuits and introducing a spatial correlation via an encoding circuit coupled to the plurality of unrolled circuits for an activity analysis of the sequential circuit, the spatial…
METHOD OF RECORDING AND REPLAYING CALL FRAMES FOR A TEST BENCH
Granted: June 12, 2014
Application Number:
20140165023
A computer-implemented method to debug testbench code of a testbench associated with a circuit design by recording a trace of call frames along with activities of the circuit design. By correlating and displaying the recorded trace of call frames, the method enables users to easily trace as execution history of subroutines executed by the testbench thereby to debug the testbench code. In addition, users can trace source code of the testbench code by using the recorded trace of call…
SEMICONDUCTOR HOLD TIME FIXING
Granted: June 12, 2014
Application Number:
20140165019
Computer implemented techniques are disclosed for fixing signal hold-time violations in semiconductor chips. Analysis includes estimation of hold-time requirements using ideal clocks. Allocation of placement regions within the design and near the macro circuits allows for later placement and wiring use during layout hold-time fixing. The placement region sizes are based on estimates of the needed buffers. Nets, within the design for detail routing, are ordered such that nets with…
MANAGING MODEL CHECKS OF SEQUENTIAL DESIGNS
Granted: June 5, 2014
Application Number:
20140157216
A method, system or computer usable program product for model checking a first circuit model including determining whether the first circuit model is functionally equivalent to one of a set of prior circuit models stored in persistent memory, and in response to determining functional equivalence, utilizing a processor to provide test results for the functionally equivalent prior circuit model.
SYSTEM AND METHOD OF EMULATING MULTIPLE CUSTOM PROTOTYPE BOARDS
Granted: June 5, 2014
Application Number:
20140157215
An emulation system integrates multiple custom prototyping boards for emulating a circuit design. A first custom prototyping board including at least one FPGA and an interface connected to a first set of wires coupling to the at least one FPGA. A second custom prototyping board includes at least one second FPGA and an interface connected to a second set of wires coupling to the at least second FPGA. An adaptor board connects to the first custom prototyping board and the second custom…
MODELING A BUS FOR A SYSTEM DESIGN INCORPORATING ONE OR MORE PROGRAMMABLE PROCESSORS
Granted: June 5, 2014
Application Number:
20140156249
Systems and methods for modeling a bus for a system design are provided. In an embodiment, the method operates by accepting a virtual bus model, wherein the model simulates behavior for a bus master and slave device, such that the model accurately simulates the timing and behavior of the transfer of data from master to slave, and, from slave to master devices. The method routes a transaction issued by the master device to the slave device. The transaction has storage for transaction…
ASYMMETRIC DENSE FLOATING GATE NONVOLATILE MEMORY WITH DECOUPLED CAPACITOR
Granted: May 29, 2014
Application Number:
20140145253
A nonvolatile memory (“NVM”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of capacitors separated from the source and drain allows for improved control over the voltage of the floating gate. This in turn allows CHEI (or IHEI) to be performed with much higher efficiency than in existing bitcells, thereby the need for a charge pump to provide current to the bitcell, ultimately…
LOW-OVERHEAD MULTI-PATTERNING DESIGN RULE CHECK
Granted: May 29, 2014
Application Number:
20140149955
Roughly described, a system enables quick and accurate depiction to a user of multi-patterning layout violations so that they may be corrected manually and in real time, and without interfering with normal manual editing process. In one embodiment, the system involves iteratively building tree structures with nodes identifying islands and arcs identifying multi-patterning spacing violations between the connected islands. The system detects coloring violations during the building of these…
